From 33078e467088c4f5d81a64777c4999329dadf982 Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Thu, 10 Sep 2020 11:06:20 +0300 Subject: [PATCH] Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. --- bddisasm/bddisasm.c | 18 + bddisasm/include/instructions.h | 16053 ++++--- bddisasm/include/mnemonics.h | 77 +- bddisasm/include/table_evex.h | 1234 +- bddisasm/include/table_root.h | 473 +- bddisasm/include/table_vex.h | 938 +- bddisasm/include/table_xop.h | 148 +- bddisasm/include/tabledefs.h | 6 +- bddisasm_test/amx/amx1_64.result | 48 +- bddisasm_test/avx/avx2_64.result | 900 +- bddisasm_test/avx/avx2gather_64.result | 30 +- bddisasm_test/avx/avx_64.result | 6594 ++- bddisasm_test/avx/f16c_64.result | 24 +- bddisasm_test/avx/fma4_64.result | 384 +- bddisasm_test/avx/fma_64.result | 576 +- bddisasm_test/avx512/avx512bitalg_64.result | 360 +- bddisasm_test/avx512/avx512bw_64.result | 10470 +++-- bddisasm_test/avx512/avx512cd_64.result | 738 +- bddisasm_test/avx512/avx512dq_64.result | 5772 ++- bddisasm_test/avx512/avx512er_64.result | 672 +- bddisasm_test/avx512/avx512f_64.result | 40596 +++++++++++------ bddisasm_test/avx512/avx512fma_64.result | 360 +- bddisasm_test/avx512/avx512pf_64.result | 48 +- bddisasm_test/avx512/avx512vbmi_64.result | 3780 +- bddisasm_test/avx512/avx512vnni_64.result | 720 +- bddisasm_test/basic/address_16.result | 51 +- bddisasm_test/basic/address_32.result | 51 +- bddisasm_test/basic/address_64.result | 105 +- bddisasm_test/basic/aes_64.result | 120 +- bddisasm_test/basic/basic1_64.result | 1605 +- bddisasm_test/basic/basic2_64.result | 447 +- bddisasm_test/basic/bmi_64.result | 156 +- bddisasm_test/basic/branch_16.result | 126 +- bddisasm_test/basic/branch_32.result | 132 +- bddisasm_test/basic/branch_64.result | 96 +- bddisasm_test/basic/cet_64 | Bin 0 -> 49 bytes bddisasm_test/basic/cet_64.asm | 13 + bddisasm_test/basic/cet_64.result | 179 + bddisasm_test/basic/enqcmd_64.result | 12 +- bddisasm_test/basic/fpu_64.result | 429 +- bddisasm_test/basic/gfni_64.result | 117 +- bddisasm_test/basic/invlpgb_64.result | 6 +- bddisasm_test/basic/misc_16.result | 147 +- bddisasm_test/basic/misc_32.result | 147 +- bddisasm_test/basic/misc_64.result | 204 +- bddisasm_test/basic/mpx_64.result | 39 +- bddisasm_test/basic/prefixes_64.result | 222 +- bddisasm_test/basic/sha_64.result | 42 +- bddisasm_test/basic/snp_64.result | 12 +- bddisasm_test/basic/stack_16.result | 96 +- bddisasm_test/basic/stack_32.result | 102 +- bddisasm_test/basic/stack_64.result | 75 +- bddisasm_test/basic/svm_64.result | 27 +- bddisasm_test/basic/system_16.result | 114 +- bddisasm_test/basic/system_32.result | 114 +- bddisasm_test/basic/system_64.result | 126 +- bddisasm_test/basic/tsx_64.result | 18 +- bddisasm_test/basic/vmx_64.result | 39 +- bddisasm_test/cet/cet_32.result | 30 +- bddisasm_test/cet/cet_64.result | 42 +- bddisasm_test/simd/3dnow_64.result | 150 +- bddisasm_test/simd/mmx_64.result | 516 +- bddisasm_test/simd/sse2_64.result | 852 +- bddisasm_test/simd/sse3_64.result | 156 +- bddisasm_test/simd/sse4_64.result | 384 +- bddisasm_test/special/amx_64.result | 396 +- bddisasm_test/special/avx2gather_1_64.result | 15 +- bddisasm_test/special/avx2gather_2_64.result | 18 +- bddisasm_test/special/avx2gather_3_64.result | 18 +- bddisasm_test/special/cr8_32.result | 6 +- bddisasm_test/special/invalid_32.result | 144 +- bddisasm_test/special/invalid_64.result | 54 +- bddisasm_test/special/long_64.result | 54 +- bddisasm_test/special/movcrdr_64.result | 108 +- bddisasm_test/special/only_32.result | 69 +- bddisasm_test/special/only_64.result | 30 +- bddisasm_test/special/regressions_32.result | 30 +- bddisasm_test/special/regressions_64.result | 33 +- bddisasm_test/tdx/tdx_64 | 1 + bddisasm_test/tdx/tdx_64.asm | 6 + bddisasm_test/tdx/tdx_64.result | 57 + disasmtool/disasmtool.c | 13 +- disasmtool_lix/dumpers.cpp | 6 + inc/bddisasm.h | 88 +- inc/constants.h | 6 + inc/version.h | 4 +- isagenerator/disasmlib.py | 18 +- isagenerator/generate_tables.py | 44 +- isagenerator/instructions/modes.dat | 35 +- isagenerator/instructions/table_0F.dat | 28 +- pybddisasm/setup.py | 2 +- 91 files changed, 64670 insertions(+), 34931 deletions(-) create mode 100644 bddisasm_test/basic/cet_64 create mode 100644 bddisasm_test/basic/cet_64.asm create mode 100644 bddisasm_test/basic/cet_64.result create mode 100644 bddisasm_test/tdx/tdx_64 create mode 100644 bddisasm_test/tdx/tdx_64.asm create mode 100644 bddisasm_test/tdx/tdx_64.result diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c index cf5e3cb..a4beb2a 100644 --- a/bddisasm/bddisasm.c +++ b/bddisasm/bddisasm.c @@ -183,6 +183,8 @@ static const uint16_t gOperandMap[] = ND_OPE_S, // ND_OPT_GPR_rBP ND_OPE_S, // ND_OPT_GPR_rSI ND_OPE_S, // ND_OPT_GPR_rDI + ND_OPE_S, // ND_OPT_GPR_rR8 + ND_OPE_S, // ND_OPT_GPR_rR9 ND_OPE_S, // ND_OPT_GPR_rR11 ND_OPE_S, // ND_OPT_SEG_CS @@ -1782,6 +1784,22 @@ NdParseOperand( operand->Info.Register.Reg = NDR_RDI; break; + case ND_OPT_GPR_rR8: + // Operand is R8. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = NDR_R8; + break; + + case ND_OPT_GPR_rR9: + // Operand is R9. + operand->Type = ND_OP_REG; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = NDR_R9; + break; + case ND_OPT_GPR_rR11: // Operand is R11. operand->Type = ND_OP_REG; diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h index 60830b5..31799e5 100644 --- a/bddisasm/include/instructions.h +++ b/bddisasm/include/instructions.h @@ -5,13 +5,14 @@ #ifndef INSTRUCTIONS_H #define INSTRUCTIONS_H -const ND_INSTRUCTION gInstructions[2561] = +const ND_INSTRUCTION gInstructions[2565] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { ND_INS_AAA, ND_CAT_DECIMAL, ND_SET_I86, 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -26,8 +27,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I" { ND_INS_AAD, ND_CAT_DECIMAL, ND_SET_I86, 1, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -43,8 +45,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:2 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" { ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 2, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -60,8 +63,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:3 Instruction:"AAS" Encoding:"0x3F"/"" { ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 3, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -76,8 +80,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:4 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -92,8 +97,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:5 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -108,8 +114,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:6 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -124,8 +131,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:7 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -140,8 +148,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:8 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -156,8 +165,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:9 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -172,8 +182,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:10 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -188,8 +199,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:11 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -204,8 +216,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:12 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + ND_PREF_HLE|ND_PREF_LOCK, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -220,8 +233,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:13 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 4, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -236,8 +250,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:14 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" { ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 5, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, 0, 0|NDR_RFLAG_CF, 0, @@ -252,8 +267,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:15 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -268,8 +284,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:16 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -284,8 +301,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:17 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -300,8 +318,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:18 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -316,8 +335,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:19 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -332,8 +352,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:20 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -348,8 +369,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:21 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -364,8 +386,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:22 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -380,8 +403,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:23 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + ND_PREF_HLE|ND_PREF_LOCK, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -396,8 +420,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:24 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 6, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -412,8 +437,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:25 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" { ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 7, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -427,8 +453,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:26 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" { ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 8, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -442,8 +469,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:27 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" { ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 9, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -457,8 +485,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:28 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" { ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 10, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -472,8 +501,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:29 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" { ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 11, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -487,8 +517,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:30 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" { ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 12, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -502,8 +533,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:31 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" { ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 13, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, 0, 0|NDR_RFLAG_OF, 0, @@ -518,8 +550,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:32 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" { ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 14, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -533,8 +566,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:33 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" { ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 15, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -548,8 +582,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:34 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" { ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 16, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -563,8 +598,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:35 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" { ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 17, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -578,8 +614,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:36 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" { ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 18, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -593,8 +630,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:37 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" { ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 19, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -609,8 +647,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:38 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" { ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 20, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -623,8 +662,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:39 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -639,8 +679,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:40 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -655,8 +696,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:41 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -671,8 +713,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:42 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -687,8 +730,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:43 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -703,8 +747,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:44 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -719,8 +764,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:45 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -735,8 +781,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:46 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -751,8 +798,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:47 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + ND_PREF_HLE|ND_PREF_LOCK, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -767,8 +815,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:48 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 21, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -783,8 +832,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:49 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" { ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 22, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -800,8 +850,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:50 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" { ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 23, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -815,8 +866,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:51 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" { ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 24, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -830,8 +882,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:52 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" { ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 25, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -845,8 +898,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:53 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" { ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 26, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -860,8 +914,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:54 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" { ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 27, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -876,8 +931,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:55 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" { ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 28, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_ZF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, @@ -893,8 +949,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:56 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" { ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 28, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -909,8 +966,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:57 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" { ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 29, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -924,8 +982,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:58 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" { ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 30, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -939,8 +998,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:59 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" { ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 31, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -954,8 +1014,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:60 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" { ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 32, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -969,8 +1030,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:61 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" { ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 33, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -984,8 +1046,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:62 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" { ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 34, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -1000,8 +1063,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:63 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" { ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 35, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -1016,8 +1080,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:64 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" { ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 36, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -1032,8 +1097,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:65 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" { ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 37, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -1048,8 +1114,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:66 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" { ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 38, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -1063,8 +1130,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:67 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" { ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 39, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -1079,8 +1147,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:68 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" { ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 40, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -1094,8 +1163,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:69 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" { ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 41, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -1110,8 +1180,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:70 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" { ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 42, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -1126,8 +1197,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:71 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" { ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 43, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, @@ -1141,8 +1213,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:72 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" { ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 44, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, @@ -1156,8 +1229,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:73 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" { ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 45, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, @@ -1171,8 +1245,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:74 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM" { ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 46, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 0, 0, 0, @@ -1186,8 +1261,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:75 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" { ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 47, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, @@ -1201,8 +1277,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:76 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" { ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, @@ -1216,8 +1293,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:77 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" { ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 48, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, @@ -1231,8 +1309,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:78 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR" { ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 49, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 0, 0, 0, @@ -1246,8 +1325,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:79 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" { ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 50, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, @@ -1261,8 +1341,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:80 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" { ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 51, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1277,8 +1358,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:81 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" { ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 52, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1293,8 +1375,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:82 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1307,8 +1390,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:83 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1321,8 +1405,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:84 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1335,8 +1420,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:85 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1349,8 +1435,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:86 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1363,8 +1450,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:87 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1377,8 +1465,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:88 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1391,8 +1480,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:89 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 53, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1405,8 +1495,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:90 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" { ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1421,8 +1512,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:91 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" { ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 54, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1437,8 +1529,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:92 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" { ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 55, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1453,8 +1546,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:93 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" { ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 55, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1469,8 +1563,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:94 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" { ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1485,8 +1580,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:95 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" { ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 56, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1501,8 +1597,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:96 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" { ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1517,8 +1614,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:97 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" { ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 57, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -1533,8 +1631,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:98 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" { ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 58, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, @@ -1550,8 +1649,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:99 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" { ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 59, + ND_PREF_BND, ND_MOD_ANY, - ND_PREF_BND, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -1567,8 +1667,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:100 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" { ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 59, + ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -1584,8 +1685,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:101 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" { ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 60, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -1602,8 +1704,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:102 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" { ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 60, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -1620,8 +1723,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:103 Instruction:"CBW" Encoding:"ds16 0x98"/"" { ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 61, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1635,8 +1739,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:104 Instruction:"CDQ" Encoding:"ds32 0x99"/"" { ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 62, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1650,8 +1755,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:105 Instruction:"CDQE" Encoding:"ds64 0x98"/"" { ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 63, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1665,8 +1771,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:106 Instruction:"CL1INVMB" Encoding:"0x0F 0x0A"/"" { ND_INS_CL1INVMB, ND_CAT_SYSTEM, ND_SET_SCC, 64, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1679,8 +1786,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:107 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" { ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 65, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 0, 0, 0, @@ -1693,8 +1801,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:108 Instruction:"CLC" Encoding:"0xF8"/"" { ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 66, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1707,8 +1816,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:109 Instruction:"CLD" Encoding:"0xFC"/"" { ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 67, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1721,8 +1831,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:110 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" { ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 68, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, 0, 0, 0, @@ -1735,8 +1846,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:111 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" { ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 69, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -1749,8 +1861,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:112 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" { ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 70, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -1763,8 +1876,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:113 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" { ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 71, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, 0, 0, 0, @@ -1777,8 +1891,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:114 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" { ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 72, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, 0, 0, 0, @@ -1791,8 +1906,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:115 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" { ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 73, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, @@ -1805,8 +1921,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:116 Instruction:"CLI" Encoding:"0xFA"/"" { ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 74, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1819,8 +1936,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:117 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" { ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 75, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0|NDR_RFLAG_CF, 0, @@ -1834,8 +1952,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:118 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" { ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 76, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1848,8 +1967,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:119 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" { ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 77, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, 0, 0, 0, @@ -1862,8 +1982,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:120 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" { ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 78, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -1876,8 +1997,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:121 Instruction:"CMC" Encoding:"0xF5"/"" { ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 79, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0, @@ -1890,8 +2012,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:122 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 80, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -1906,8 +2029,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:123 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 81, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF, 0, 0, @@ -1922,8 +2046,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:124 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 82, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -1938,8 +2063,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:125 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 83, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -1954,8 +2080,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:126 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 84, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -1970,8 +2097,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:127 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 85, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF, 0, 0, @@ -1986,8 +2114,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:128 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 86, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -2002,8 +2131,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:129 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 87, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -2018,8 +2148,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:130 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 88, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_OF, 0, 0, @@ -2034,8 +2165,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:131 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 89, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_PF, 0, 0, @@ -2050,8 +2182,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:132 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 90, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF, 0, 0, @@ -2066,8 +2199,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:133 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 91, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_ZF, 0, 0, @@ -2082,8 +2216,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:134 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_OF, 0, 0, @@ -2098,8 +2233,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:135 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_PF, 0, 0, @@ -2114,8 +2250,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:136 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF, 0, 0, @@ -2130,8 +2267,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:137 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_ZF, 0, 0, @@ -2146,8 +2284,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:138 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2162,8 +2301,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:139 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2178,8 +2318,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:140 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2194,8 +2335,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:141 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2210,8 +2352,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:142 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2226,8 +2369,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:143 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2242,8 +2386,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:144 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2258,8 +2403,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:145 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2274,8 +2420,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:146 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2290,8 +2437,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:147 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 96, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2306,8 +2454,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:148 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 97, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2322,8 +2471,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:149 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 98, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -2338,8 +2488,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:150 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2356,8 +2507,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:151 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 99, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2375,8 +2527,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:152 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 100, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2391,8 +2544,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:153 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2409,8 +2563,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:154 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 100, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2428,8 +2583,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:155 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2446,8 +2602,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:156 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 101, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2465,8 +2622,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:157 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 102, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -2481,8 +2639,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:158 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2499,8 +2658,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:159 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 103, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2518,8 +2678,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:160 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" { ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2535,8 +2696,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:161 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" { ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 104, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -2552,8 +2714,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:162 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" { ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 105, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, + 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 0, 0|NDR_RFLAG_ZF, 0, @@ -2571,8 +2734,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:163 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" { ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 106, + ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, - ND_PREF_LOCK|ND_PREF_HLE, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, + 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 0, 0|NDR_RFLAG_ZF, 0, @@ -2590,8 +2754,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:164 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" { ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 107, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -2606,8 +2771,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:165 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" { ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 108, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -2622,8 +2788,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:166 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" { ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 109, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, @@ -2639,8 +2806,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:167 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" { ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 110, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2653,8 +2821,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:168 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" { ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 111, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2667,8 +2836,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:169 Instruction:"CQO" Encoding:"ds64 0x99"/"" { ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 112, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2682,8 +2852,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:170 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, @@ -2697,8 +2868,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:171 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, @@ -2712,8 +2884,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:172 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, @@ -2727,8 +2900,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:173 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 113, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, @@ -2742,8 +2916,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:174 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" { ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 114, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2757,8 +2932,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:175 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" { ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 115, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2772,8 +2948,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:176 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" { ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 116, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2787,8 +2964,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:177 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" { ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 117, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2802,8 +2980,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:178 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" { ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 118, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2817,8 +2996,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:179 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" { ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 119, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2832,8 +3012,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:180 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" { ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 120, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -2847,8 +3028,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:181 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" { ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 121, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2862,8 +3044,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:182 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" { ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 122, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2877,8 +3060,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:183 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" { ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 123, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -2892,8 +3076,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:184 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" { ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 124, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2907,8 +3092,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:185 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" { ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 125, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2922,8 +3108,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:186 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" { ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 126, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2937,8 +3124,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:187 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" { ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 127, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -2952,8 +3140,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:188 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" { ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 128, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2967,8 +3156,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:189 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" { ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 129, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -2982,8 +3172,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:190 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" { ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 130, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -2997,8 +3188,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:191 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" { ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 131, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -3012,8 +3204,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:192 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" { ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 132, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -3027,8 +3220,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:193 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" { ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 133, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -3042,8 +3236,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:194 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" { ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 134, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -3057,8 +3252,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:195 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" { ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 135, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -3072,8 +3268,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:196 Instruction:"CWD" Encoding:"ds16 0x99"/"" { ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 136, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3087,8 +3284,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:197 Instruction:"CWDE" Encoding:"ds32 0x98"/"" { ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 137, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3102,8 +3300,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:198 Instruction:"DAA" Encoding:"0x27"/"" { ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 138, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF, 0|NDR_RFLAG_OF, @@ -3117,8 +3316,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:199 Instruction:"DAS" Encoding:"0x2F"/"" { ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 139, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_OF, @@ -3132,8 +3332,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:200 Instruction:"DEC Zv" Encoding:"0x48"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3147,8 +3348,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:201 Instruction:"DEC Zv" Encoding:"0x49"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3162,8 +3364,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:202 Instruction:"DEC Zv" Encoding:"0x4A"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3177,8 +3380,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:203 Instruction:"DEC Zv" Encoding:"0x4B"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3192,8 +3396,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:204 Instruction:"DEC Zv" Encoding:"0x4C"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3207,8 +3412,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:205 Instruction:"DEC Zv" Encoding:"0x4D"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3222,8 +3428,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:206 Instruction:"DEC Zv" Encoding:"0x4E"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3237,8 +3444,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:207 Instruction:"DEC Zv" Encoding:"0x4F"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3252,8 +3460,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:208 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3267,8 +3476,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:209 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 140, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -3282,8 +3492,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:210 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" { ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 141, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3296,8 +3507,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:211 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" { ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -3314,8 +3526,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:212 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" { ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 142, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -3331,8 +3544,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:213 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" { ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 143, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -3346,8 +3560,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:214 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" { ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 144, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -3361,8 +3576,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:215 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" { ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 145, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -3376,8 +3592,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:216 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" { ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 146, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -3391,8 +3608,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:217 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" { ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 147, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3405,8 +3623,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:218 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" { ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 148, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -3421,8 +3640,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:219 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" { ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 149, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -3437,8 +3657,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:220 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" { ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 150, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, 0, 0, 0, @@ -3451,8 +3672,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:221 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" { ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 151, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 0, 0, 0, @@ -3468,8 +3690,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:222 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" { ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 152, - ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 0, 0, 0, @@ -3485,8 +3708,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:223 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" { ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 153, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 0, 0, 0, @@ -3502,8 +3726,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:224 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" { ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 154, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, 0, 0, 0, @@ -3516,8 +3741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:225 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" { ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 155, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, 0, 0, 0, @@ -3530,8 +3756,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:226 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" { ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 156, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 0, 0|NDR_RFLAG_ZF, 0, @@ -3546,8 +3773,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:227 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" { ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 157, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 0, 0|NDR_RFLAG_ZF, 0, @@ -3562,8 +3790,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:228 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" { ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 158, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3580,8 +3809,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:229 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" { ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 159, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -3596,8 +3826,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:230 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" { ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, @@ -3612,8 +3843,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:231 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" { ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 160, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, @@ -3627,8 +3859,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:232 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" { ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 161, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3641,8 +3874,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:233 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" { ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 162, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3655,8 +3889,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:234 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3671,8 +3906,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:235 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3687,8 +3923,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:236 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3703,8 +3940,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:237 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 163, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3719,8 +3957,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:238 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" { ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 164, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3735,8 +3974,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:239 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" { ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 165, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3751,8 +3991,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:240 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" { ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 166, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3767,8 +4008,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:241 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" { ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 167, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3781,8 +4023,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:242 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" { ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 168, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -3798,8 +4041,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:243 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" { ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 169, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -3815,8 +4059,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:244 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" { ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 170, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -3832,8 +4077,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:245 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" { ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 171, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -3849,8 +4095,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:246 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" { ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 172, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -3866,8 +4113,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:247 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" { ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 173, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -3883,8 +4131,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:248 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" { ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 174, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -3900,8 +4149,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:249 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" { ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 175, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -3917,8 +4167,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:250 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3933,8 +4184,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:251 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3949,8 +4201,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:252 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3965,8 +4218,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:253 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 176, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -3981,8 +4235,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:254 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" { ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 177, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -3998,8 +4253,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:255 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" { ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 178, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -4015,8 +4271,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:256 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4031,8 +4288,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:257 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4047,8 +4305,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:258 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4063,8 +4322,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:259 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4079,8 +4339,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:260 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 179, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4095,8 +4356,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:261 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" { ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 180, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4109,8 +4371,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:262 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" { ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 181, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4123,8 +4386,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:263 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" { ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 182, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4137,8 +4401,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:264 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4153,8 +4418,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:265 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4169,8 +4435,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:266 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4185,8 +4452,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:267 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 183, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4201,8 +4469,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:268 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" { ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 184, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4217,8 +4486,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:269 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4233,8 +4503,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:270 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4249,8 +4520,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:271 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4265,8 +4537,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:272 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 185, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4281,8 +4554,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:273 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" { ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 186, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4297,8 +4571,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:274 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" { ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 187, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, 0, 0, 0, @@ -4311,8 +4586,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:275 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" { ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 188, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4326,8 +4602,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:276 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" { ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 189, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4341,8 +4618,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:277 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" { ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4357,8 +4635,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:278 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" { ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 190, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4373,8 +4652,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:279 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" { ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4389,8 +4669,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:280 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" { ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 191, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4405,8 +4686,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:281 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" { ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4421,8 +4703,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:282 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" { ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 192, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4437,8 +4720,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:283 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" { ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4453,8 +4737,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:284 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" { ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 193, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4469,8 +4754,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:285 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" { ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4485,8 +4771,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:286 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" { ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 194, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4501,8 +4788,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:287 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" { ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4517,8 +4805,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:288 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" { ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4533,8 +4822,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:289 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" { ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 195, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4549,8 +4839,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:290 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" { ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4565,8 +4856,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:291 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" { ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 196, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4581,8 +4873,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:292 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" { ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 197, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4595,8 +4888,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:293 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" { ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4611,8 +4905,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:294 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" { ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 198, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4627,8 +4922,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:295 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" { ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4643,8 +4939,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:296 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" { ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4659,8 +4956,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:297 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" { ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 199, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4675,8 +4973,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:298 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" { ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4691,8 +4990,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:299 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" { ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4707,8 +5007,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:300 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" { ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 200, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4723,8 +5024,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:301 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" { ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4739,8 +5041,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:302 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" { ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 201, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4755,8 +5058,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:303 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" { ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4771,8 +5075,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:304 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" { ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 202, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4787,8 +5092,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:305 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4803,8 +5109,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:306 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4819,8 +5126,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:307 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4835,8 +5143,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:308 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 203, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4851,8 +5160,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:309 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" { ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 204, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4865,8 +5175,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:310 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" { ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 205, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4881,8 +5192,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:311 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" { ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 206, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4896,8 +5208,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:312 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" { ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 207, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4910,8 +5223,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:313 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" { ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 208, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4924,8 +5238,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:314 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" { ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 209, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4938,8 +5253,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:315 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" { ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 210, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4952,8 +5268,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:316 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" { ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 211, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4966,8 +5283,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:317 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" { ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 212, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4980,8 +5298,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:318 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -4996,8 +5315,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:319 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5012,8 +5332,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:320 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5028,8 +5349,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:321 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 213, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5044,8 +5366,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:322 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" { ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 214, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5060,8 +5383,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:323 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" { ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 215, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5074,8 +5398,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:324 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" { ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 216, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5088,8 +5413,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:325 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" { ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 217, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5104,8 +5430,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:326 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" { ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5118,8 +5445,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:327 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" { ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5132,8 +5460,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:328 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" { ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 218, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5146,8 +5475,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:329 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" { ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 219, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5163,8 +5493,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:330 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" { ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 220, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5179,8 +5510,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:331 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" { ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 221, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5194,8 +5526,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:332 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" { ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5209,8 +5542,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:333 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" { ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 222, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5224,8 +5558,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:334 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" { ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 223, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5238,8 +5573,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:335 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" { ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 224, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5252,8 +5588,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:336 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" { ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 225, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5266,8 +5603,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:337 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" { ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 226, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5280,8 +5618,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:338 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" { ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 227, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5294,8 +5633,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:339 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" { ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 228, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5308,8 +5648,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:340 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" { ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 229, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5323,8 +5664,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:341 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" { ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 230, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5337,8 +5679,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:342 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" { ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 231, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5351,8 +5694,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:343 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" { ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 232, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5365,8 +5709,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:344 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" { ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 233, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5379,8 +5724,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:345 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" { ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5395,8 +5741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:346 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" { ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5411,8 +5758,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:347 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" { ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 234, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5427,8 +5775,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:348 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" { ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 235, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5441,8 +5790,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:349 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5457,8 +5807,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:350 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5473,8 +5824,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:351 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5489,8 +5841,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:352 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5505,8 +5858,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:353 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5521,8 +5875,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:354 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 236, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5537,8 +5892,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:355 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" { ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 237, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5553,8 +5909,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:356 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" { ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 238, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5567,8 +5924,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:357 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5583,8 +5941,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:358 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5599,8 +5958,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:359 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5615,8 +5975,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:360 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 239, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5631,8 +5992,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:361 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" { ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 240, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5647,8 +6009,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:362 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5663,8 +6026,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:363 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5679,8 +6043,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:364 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5695,8 +6060,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:365 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 241, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5711,8 +6077,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:366 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" { ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 242, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5727,8 +6094,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:367 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" { ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 243, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5741,8 +6109,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:368 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" { ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 244, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5757,8 +6126,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:369 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" { ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 245, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -5774,8 +6144,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:370 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" { ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 246, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -5791,8 +6162,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:371 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" { ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 247, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5807,8 +6179,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:372 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" { ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 248, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5821,8 +6194,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:373 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" { ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 249, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5835,8 +6209,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:374 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" { ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5851,8 +6226,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:375 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" { ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5867,8 +6243,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:376 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" { ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 250, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5883,8 +6260,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:377 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" { ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 251, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, @@ -5898,8 +6276,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:378 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" { ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 252, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, @@ -5913,8 +6292,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:379 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" { ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 253, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, @@ -5928,8 +6308,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:380 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" { ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 254, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, @@ -5943,8 +6324,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:381 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" { ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 255, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5957,8 +6339,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:382 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" { ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 256, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5971,8 +6354,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:383 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" { ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 257, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -5985,8 +6369,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:384 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" { ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 258, - ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, 0, 0, 0, @@ -6000,8 +6385,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:385 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" { ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 259, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, @@ -6016,8 +6402,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:386 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" { ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 260, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, @@ -6032,8 +6419,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:387 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" { ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 261, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, @@ -6047,8 +6435,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:388 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" { ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 262, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -6062,8 +6451,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:389 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" { ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 263, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -6077,8 +6467,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:390 Instruction:"HLT" Encoding:"0xF4"/"" { ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 264, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -6091,8 +6482,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:391 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" { ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 265, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -6106,8 +6498,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:392 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" { ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 266, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -6121,8 +6514,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:393 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" { ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 267, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6139,8 +6533,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:394 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" { ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 267, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -6156,8 +6551,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:395 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -6172,8 +6568,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:396 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -6189,8 +6586,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:397 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -6206,8 +6604,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:398 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -6223,8 +6622,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:399 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 268, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -6240,8 +6640,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:400 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6256,8 +6657,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:401 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6272,8 +6674,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:402 Instruction:"IN AL,DX" Encoding:"0xEC"/"" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6288,8 +6691,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:403 Instruction:"IN eAX,DX" Encoding:"0xED"/"" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 269, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6304,8 +6708,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:404 Instruction:"INC Zv" Encoding:"0x40"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6319,8 +6724,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:405 Instruction:"INC Zv" Encoding:"0x41"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6334,8 +6740,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:406 Instruction:"INC Zv" Encoding:"0x42"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6349,8 +6756,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:407 Instruction:"INC Zv" Encoding:"0x43"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6364,8 +6772,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:408 Instruction:"INC Zv" Encoding:"0x44"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6379,8 +6788,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:409 Instruction:"INC Zv" Encoding:"0x45"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6394,8 +6804,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:410 Instruction:"INC Zv" Encoding:"0x46"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6409,8 +6820,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:411 Instruction:"INC Zv" Encoding:"0x47"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6424,8 +6836,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:412 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6439,8 +6852,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:413 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 270, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -6454,8 +6868,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:414 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" { ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 271, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, @@ -6470,8 +6885,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:415 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" { ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 272, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, @@ -6486,8 +6902,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:416 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6503,8 +6920,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:417 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 273, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6521,8 +6939,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:418 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6538,8 +6957,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:419 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 274, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6556,8 +6976,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:420 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" { ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 275, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -6572,8 +6993,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:421 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" { ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 275, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -6588,8 +7010,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:422 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" { ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 276, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, @@ -6605,8 +7028,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:423 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" { ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 276, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, @@ -6620,8 +7044,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:424 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6637,8 +7062,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:425 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 277, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -6655,8 +7081,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:426 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" { ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 278, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, @@ -6674,8 +7101,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:427 Instruction:"INT1" Encoding:"0xF1"/"" { ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 279, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, @@ -6691,8 +7119,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:428 Instruction:"INT3" Encoding:"0xCC"/"" { ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 280, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, @@ -6709,8 +7138,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:429 Instruction:"INTO" Encoding:"0xCE"/"" { ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 281, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, @@ -6727,8 +7157,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:430 Instruction:"INVD" Encoding:"0x0F 0x08"/"" { ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 282, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, @@ -6741,8 +7172,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:431 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" { ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 283, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -6757,8 +7189,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:432 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" { ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 284, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -6771,8 +7204,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:433 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" { ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 285, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, @@ -6786,8 +7220,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:434 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" { ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 286, - ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 0, 0, 0, @@ -6802,8 +7237,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:435 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" { ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 287, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, 0, 0, 0, @@ -6817,8 +7253,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:436 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" { ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 288, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -6833,8 +7270,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:437 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" { ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 289, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, @@ -6851,8 +7289,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:438 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" { ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 290, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, @@ -6869,8 +7308,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:439 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" { ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 291, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, @@ -6887,8 +7327,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:440 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -6903,8 +7344,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:441 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 292, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -6919,8 +7361,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:442 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -6935,8 +7378,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:443 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 293, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -6951,8 +7395,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:444 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" { ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 294, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -6967,8 +7412,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:445 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" { ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 295, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -6983,8 +7429,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:446 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -6999,8 +7446,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:447 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 296, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -7015,8 +7463,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:448 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -7031,8 +7480,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:449 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 297, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -7047,8 +7497,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:450 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" { ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_PREF_BND, ND_MOD_ANY, - ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -7062,8 +7513,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:451 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" { ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_PREF_BND, ND_MOD_ANY, - ND_PREF_BND, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -7077,8 +7529,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:452 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" { ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 298, + ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_DNT, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -7092,8 +7545,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:453 Instruction:"JMPE Ev" Encoding:"0x0F 0x00 /6"/"M" { ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 299, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, @@ -7107,8 +7561,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:454 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" { ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 299, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -7122,8 +7577,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:455 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" { ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 300, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -7138,8 +7594,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:456 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" { ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 300, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -7154,8 +7611,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:457 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -7170,8 +7628,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:458 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 301, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -7186,8 +7645,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:459 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -7202,8 +7662,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:460 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 302, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -7218,8 +7679,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:461 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -7234,8 +7696,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:462 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 303, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -7250,8 +7713,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:463 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -7266,8 +7730,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:464 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 304, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -7282,8 +7747,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:465 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, @@ -7298,8 +7764,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:466 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 305, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, @@ -7314,8 +7781,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:467 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -7330,8 +7798,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:468 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 306, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -7346,8 +7815,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:469 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, @@ -7362,8 +7832,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:470 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 307, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, @@ -7378,8 +7849,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:471 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -7394,8 +7866,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:472 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 308, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -7410,8 +7883,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:473 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, @@ -7426,8 +7900,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:474 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 309, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, @@ -7442,8 +7917,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:475 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -7458,8 +7934,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:476 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 310, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -7474,8 +7951,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:477 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" { ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 311, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -7490,8 +7968,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:478 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, @@ -7506,8 +7985,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:479 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 312, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, @@ -7522,8 +8002,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:480 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -7538,8 +8019,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:481 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 313, + ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, - ND_PREF_BND|ND_PREF_BHINT, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -7554,8 +8036,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:482 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 314, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7570,8 +8053,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:483 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 315, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7586,8 +8070,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:484 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 316, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7602,8 +8087,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:485 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 317, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7618,8 +8104,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:486 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 318, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7634,8 +8121,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:487 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 319, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7650,8 +8138,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:488 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 320, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7666,8 +8155,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:489 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 321, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7682,8 +8172,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:490 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 322, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7698,8 +8189,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:491 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 323, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -7714,8 +8206,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:492 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 324, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7730,8 +8223,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:493 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 325, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -7746,8 +8240,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:494 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" { ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 326, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -7761,8 +8256,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:495 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" { ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 327, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -7776,8 +8272,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:496 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7791,8 +8288,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:497 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7806,8 +8304,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:498 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7821,8 +8320,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:499 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7836,8 +8336,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:500 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 328, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -7851,8 +8352,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:501 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7866,8 +8368,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:502 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7881,8 +8384,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:503 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7896,8 +8400,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:504 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7911,8 +8416,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:505 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 329, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7926,8 +8432,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:506 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7941,8 +8448,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:507 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7956,8 +8464,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:508 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7971,8 +8480,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:509 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -7986,8 +8496,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:510 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 330, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8001,8 +8512,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:511 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8016,8 +8528,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:512 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8031,8 +8544,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:513 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8046,8 +8560,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:514 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8061,8 +8576,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:515 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 331, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8076,8 +8592,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:516 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 332, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8091,8 +8608,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:517 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 333, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8106,8 +8624,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:518 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 334, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8121,8 +8640,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:519 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 335, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8136,8 +8656,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:520 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 336, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8152,8 +8673,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:521 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 337, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8168,8 +8690,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:522 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 338, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8184,8 +8707,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:523 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 339, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -8200,8 +8724,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:524 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 340, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -8216,8 +8741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:525 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 341, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -8232,8 +8758,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:526 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 342, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -8248,8 +8775,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:527 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 343, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8264,8 +8792,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:528 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 344, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8280,8 +8809,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:529 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 345, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8296,8 +8826,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:530 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 346, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8312,8 +8843,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:531 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 347, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8328,8 +8860,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:532 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 348, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8344,8 +8877,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:533 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 349, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8360,8 +8894,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:534 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 350, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8376,8 +8911,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:535 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 351, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8392,8 +8928,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:536 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 352, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8407,8 +8944,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:537 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 353, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8422,8 +8960,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:538 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 354, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8437,8 +8976,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:539 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 355, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8452,8 +8992,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:540 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" { ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 356, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8468,8 +9009,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:541 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" { ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 357, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8484,8 +9026,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:542 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" { ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 358, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8500,8 +9043,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:543 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 359, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8516,8 +9060,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:544 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 360, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8532,8 +9077,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:545 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 361, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8548,8 +9094,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:546 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 362, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8564,8 +9111,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:547 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 363, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, @@ -8580,8 +9128,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:548 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 364, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8596,8 +9145,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:549 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 365, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, @@ -8612,8 +9162,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:550 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 366, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, @@ -8628,8 +9179,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:551 Instruction:"LAHF" Encoding:"0x9F"/"" { ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 367, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0, 0, @@ -8643,8 +9195,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:552 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" { ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 368, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -8659,8 +9212,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:553 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" { ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 368, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -8675,8 +9229,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:554 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" { ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 369, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -8690,8 +9245,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:555 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" { ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 370, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -8705,8 +9261,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:556 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" { ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 371, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, @@ -8721,8 +9278,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:557 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" { ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 372, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -8735,8 +9293,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:558 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" { ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 373, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8750,8 +9309,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:559 Instruction:"LEAVE" Encoding:"0xC9"/"" { ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 374, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -8767,8 +9327,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:560 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" { ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 375, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, @@ -8783,8 +9344,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:561 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" { ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 376, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -8797,8 +9359,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:562 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" { ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 377, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8813,8 +9376,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:563 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" { ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 378, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8828,8 +9392,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:564 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" { ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 379, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8844,8 +9409,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:565 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" { ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 380, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8859,8 +9425,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:566 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" { ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 381, - ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8874,8 +9441,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:567 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" { ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 382, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, @@ -8888,8 +9456,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:568 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" { ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 383, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -8903,8 +9472,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:569 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -8920,8 +9490,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:570 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 384, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -8938,8 +9509,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:571 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -8955,8 +9527,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:572 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 385, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -8973,8 +9546,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:573 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -8990,8 +9564,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:574 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 386, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -9008,8 +9583,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:575 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -9025,8 +9601,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:576 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 387, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -9043,8 +9620,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:577 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" { ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 388, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -9060,8 +9638,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:578 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" { ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 389, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -9077,8 +9656,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:579 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" { ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 390, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -9094,8 +9674,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:580 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" { ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -9110,8 +9691,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:581 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" { ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 391, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -9126,8 +9708,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:582 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" { ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 392, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9142,8 +9725,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:583 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" { ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 393, - ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9157,8 +9741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:584 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" { ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 394, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, @@ -9173,8 +9758,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:585 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" { ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 395, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, @@ -9189,8 +9775,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:586 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" { ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 396, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -9205,8 +9792,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:587 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" { ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 397, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -9221,8 +9809,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:588 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" { ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 398, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -9237,8 +9826,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:589 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" { ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 399, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -9252,8 +9842,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:590 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" { ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 400, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -9267,8 +9858,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:591 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" { ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 401, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -9282,8 +9874,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:592 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" { ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 402, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -9297,8 +9890,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:593 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" { ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 403, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, 0, 0|NDR_RFLAG_CF, 0, @@ -9311,8 +9905,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:594 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" { ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 404, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -9325,8 +9920,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:595 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" { ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 405, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -9340,8 +9936,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:596 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" { ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 406, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -9355,8 +9952,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:597 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" { ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 407, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -9370,8 +9968,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:598 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" { ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 408, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -9385,8 +9984,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:599 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" { ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 409, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 0, 0, 0, @@ -9401,8 +10001,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:600 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" { ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 410, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9417,8 +10018,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:601 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" { ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 411, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9431,8 +10033,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:602 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" { ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9446,8 +10049,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:603 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" { ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9461,8 +10065,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:604 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" { ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 412, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9476,8 +10081,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:605 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" { ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 412, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9491,8 +10097,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:606 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" { ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9506,8 +10113,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:607 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" { ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 412, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9521,8 +10129,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:608 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9536,8 +10145,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:609 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9551,8 +10161,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:610 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9566,8 +10177,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:611 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9581,8 +10193,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:612 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9596,8 +10209,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:613 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9611,8 +10225,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:614 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9626,8 +10241,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:615 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9641,8 +10257,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:616 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9656,8 +10273,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:617 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9671,8 +10289,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:618 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9686,8 +10305,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:619 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9701,8 +10321,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:620 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9716,8 +10337,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:621 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9731,8 +10353,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:622 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9746,8 +10369,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:623 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9761,8 +10385,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:624 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9776,8 +10401,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:625 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9791,8 +10417,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:626 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9806,8 +10433,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:627 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9821,8 +10449,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:628 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9836,8 +10465,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:629 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9851,8 +10481,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:630 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9866,8 +10497,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:631 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9881,8 +10513,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:632 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9896,8 +10529,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:633 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9911,8 +10545,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:634 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9926,8 +10561,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:635 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9941,8 +10577,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:636 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9956,8 +10593,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:637 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 412, + ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -9971,8 +10609,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:638 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" { ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -9986,8 +10625,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:639 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" { ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 413, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10001,8 +10641,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:640 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" { ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10016,8 +10657,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:641 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" { ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 414, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10031,8 +10673,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:642 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, @@ -10046,8 +10689,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:643 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, @@ -10061,8 +10705,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:644 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, @@ -10076,8 +10721,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:645 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 415, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, @@ -10091,8 +10737,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:646 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -10106,8 +10753,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:647 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10121,8 +10769,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:648 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 416, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -10136,8 +10785,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:649 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 416, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10151,8 +10801,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:650 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" { ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 417, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -10166,8 +10817,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:651 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" { ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 418, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, 0, 0, 0, @@ -10181,8 +10833,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:652 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" { ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 419, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, 0, 0, 0, @@ -10196,8 +10849,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:653 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" { ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 420, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10211,8 +10865,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:654 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" { ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10226,8 +10881,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:655 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" { ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 421, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10241,8 +10897,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:656 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" { ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10256,8 +10913,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:657 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" { ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 422, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10271,8 +10929,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:658 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" { ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 423, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10286,8 +10945,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:659 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" { ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10301,8 +10961,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:660 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" { ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 424, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10316,8 +10977,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:661 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" { ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10331,8 +10993,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:662 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" { ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 425, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10346,8 +11009,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:663 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" { ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 426, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10361,8 +11025,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:664 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" { ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10376,8 +11041,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:665 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" { ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 427, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10391,8 +11057,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:666 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" { ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 428, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10406,8 +11073,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:667 Instruction:"MOVMSKPD Gd,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" { ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 429, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10421,8 +11089,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:668 Instruction:"MOVMSKPS Gd,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" { ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 430, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10436,8 +11105,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:669 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" { ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 431, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10451,8 +11121,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:670 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" { ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 432, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -10466,8 +11137,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:671 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" { ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 433, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -10481,8 +11153,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:672 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 434, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10496,8 +11169,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:673 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 435, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10511,8 +11185,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:674 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" { ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 436, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -10526,8 +11201,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:675 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 437, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, @@ -10541,8 +11217,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:676 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 438, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, @@ -10556,8 +11233,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:677 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -10571,8 +11249,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:678 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10586,8 +11265,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:679 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -10601,8 +11281,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:680 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -10616,8 +11297,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:681 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10631,8 +11313,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:682 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10646,8 +11329,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:683 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -10661,8 +11345,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:684 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 439, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10676,8 +11361,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:685 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" { ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 440, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10691,8 +11377,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:686 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10709,8 +11396,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:687 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 441, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10728,8 +11416,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:688 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" { ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10743,8 +11432,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:689 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" { ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 442, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10758,8 +11448,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:690 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10776,8 +11467,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:691 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 442, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10795,8 +11487,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:692 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" { ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 443, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -10810,8 +11503,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:693 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" { ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 444, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, @@ -10825,8 +11519,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:694 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10843,8 +11538,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:695 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 445, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10862,8 +11558,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:696 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" { ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 446, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10877,8 +11574,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:697 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" { ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 446, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -10892,8 +11590,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:698 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10910,8 +11609,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:699 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 447, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -10929,8 +11629,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:700 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" { ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 448, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -10944,8 +11645,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:701 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" { ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 448, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -10959,8 +11661,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:702 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" { ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 449, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0, 0, @@ -10974,8 +11677,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:703 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" { ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -10989,8 +11693,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:704 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" { ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 450, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -11004,8 +11709,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:705 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" { ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 451, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -11019,8 +11725,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:706 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" { ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 451, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -11034,8 +11741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:707 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" { ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 452, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11049,8 +11757,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:708 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" { ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 452, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11064,8 +11773,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:709 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" { ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 453, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -11080,8 +11790,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:710 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" { ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 454, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -11097,8 +11808,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:711 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" { ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 454, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, @@ -11114,8 +11826,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:712 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" { ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 455, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -11129,8 +11842,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:713 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" { ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 456, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -11144,8 +11858,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:714 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" { ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 457, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -11159,8 +11874,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:715 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" { ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 458, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -11174,8 +11890,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:716 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" { ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 459, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -11191,8 +11908,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:717 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" { ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 460, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 0, 0, 0, @@ -11206,8 +11924,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:718 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" { ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 461, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11222,8 +11941,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:719 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" { ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 462, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -11237,8 +11957,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:720 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" { ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 462, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -11252,8 +11973,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:721 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11267,8 +11989,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:722 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11282,8 +12005,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:723 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11297,8 +12021,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:724 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11312,8 +12037,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:725 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11327,8 +12053,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:726 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11342,8 +12069,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:727 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11357,8 +12085,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:728 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11372,8 +12101,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:729 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11386,8 +12116,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:730 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11400,8 +12131,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:731 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11414,8 +12146,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:732 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11428,8 +12161,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:733 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11442,8 +12176,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:734 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11456,8 +12191,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:735 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11470,8 +12206,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:736 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11484,8 +12221,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:737 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11498,8 +12236,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:738 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1A /r"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11513,8 +12252,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:739 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11528,8 +12268,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:740 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11543,8 +12284,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:741 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11558,8 +12300,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:742 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11573,8 +12316,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:743 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11588,8 +12332,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:744 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11603,8 +12348,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:745 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11618,8 +12364,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:746 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11633,8 +12380,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:747 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11648,8 +12396,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:748 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11663,8 +12412,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:749 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11678,8 +12428,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:750 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11693,8 +12444,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:751 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11708,8 +12460,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:752 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11723,8 +12476,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:753 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11738,8 +12492,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:754 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11753,8 +12508,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:755 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11768,8 +12524,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:756 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11783,8 +12540,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11798,8 +12556,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:758 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11813,8 +12572,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:759 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11828,8 +12588,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:760 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11843,8 +12604,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:761 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11858,8 +12620,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:762 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11873,8 +12636,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:763 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11888,8 +12652,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:764 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11903,8 +12668,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:765 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11918,8 +12684,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:766 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11933,8 +12700,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:767 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11948,8 +12716,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:768 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11963,8 +12732,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:769 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11978,8 +12748,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:770 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -11993,8 +12764,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:771 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -12008,8 +12780,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:772 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -12023,8 +12796,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:773 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -12038,8 +12812,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:774 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -12053,8 +12828,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:775 Instruction:"NOP" Encoding:"0x90"/"" { ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 463, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -12067,8 +12843,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:776 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" { ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -12081,8 +12858,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:777 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" { ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 464, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -12095,8 +12873,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:778 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12111,8 +12890,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:779 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12127,8 +12907,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:780 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12143,8 +12924,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:781 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12159,8 +12941,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:782 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12175,8 +12958,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:783 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12191,8 +12975,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:784 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12207,8 +12992,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:785 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12223,8 +13009,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:786 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + ND_PREF_HLE|ND_PREF_LOCK, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12239,8 +13026,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:787 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 465, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -12255,8 +13043,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:788 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" { ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 466, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12270,8 +13059,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:789 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" { ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 467, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -12285,8 +13075,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:790 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12301,8 +13092,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:791 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12317,8 +13109,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:792 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12333,8 +13126,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:793 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 468, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12349,8 +13143,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:794 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12366,8 +13161,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:795 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 469, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12384,8 +13180,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:796 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12401,8 +13198,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:797 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 470, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12419,8 +13217,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:798 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12436,8 +13235,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:799 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 471, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + ND_PREF_REP, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, @@ -12454,8 +13254,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:800 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" { ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 472, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -12469,8 +13270,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:801 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" { ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 472, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -12484,8 +13286,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:802 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" { ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 473, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -12499,8 +13302,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:803 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" { ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 473, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -12514,8 +13318,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:804 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" { ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 474, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -12529,8 +13334,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:805 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" { ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 474, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -12544,8 +13350,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:806 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" { ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 475, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12559,8 +13366,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:807 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" { ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 475, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12574,8 +13382,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:808 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" { ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 476, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12589,8 +13398,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:809 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" { ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 476, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12604,8 +13414,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:810 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" { ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 477, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -12619,8 +13430,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:811 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" { ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 478, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12634,8 +13446,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:812 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" { ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 478, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12649,8 +13462,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:813 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" { ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 479, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12664,8 +13478,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:814 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" { ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 479, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12679,8 +13494,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:815 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" { ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 480, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12694,8 +13510,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:816 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" { ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 480, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12709,8 +13526,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:817 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" { ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 481, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -12724,8 +13542,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:818 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" { ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 481, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12739,8 +13558,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:819 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" { ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 482, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12754,8 +13574,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:820 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" { ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 482, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12769,8 +13590,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:821 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" { ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 483, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12784,8 +13606,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:822 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" { ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 483, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12799,8 +13622,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:823 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" { ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 484, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12814,8 +13638,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:824 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" { ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 484, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12829,8 +13654,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:825 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" { ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 485, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12844,8 +13670,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:826 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" { ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 485, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12859,8 +13686,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:827 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" { ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 486, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12874,8 +13702,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:828 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" { ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 486, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12889,8 +13718,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:829 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" { ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 487, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -12905,8 +13735,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:830 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" { ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 487, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -12921,8 +13752,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:831 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" { ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 488, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12936,8 +13768,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:832 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" { ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 488, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12951,8 +13784,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:833 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" { ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 489, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -12966,8 +13800,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:834 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" { ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 489, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -12981,8 +13816,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:835 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" { ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 490, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -12995,8 +13831,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:836 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" { ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 491, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13010,8 +13847,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:837 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" { ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 491, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13025,8 +13863,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:838 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" { ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 492, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13040,8 +13879,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:839 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" { ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 493, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13055,8 +13895,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:840 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" { ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 493, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13070,8 +13911,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:841 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" { ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 494, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13086,8 +13928,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:842 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" { ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 495, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13102,8 +13945,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:843 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" { ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 496, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, 0, 0, 0, @@ -13118,8 +13962,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:844 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" { ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 497, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13133,8 +13978,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:845 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" { ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 497, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13148,8 +13994,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:846 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" { ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 498, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13163,8 +14010,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:847 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" { ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 498, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13178,8 +14026,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:848 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" { ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 499, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13193,8 +14042,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:849 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" { ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 500, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13208,8 +14058,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:850 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" { ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 500, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13223,8 +14074,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:851 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" { ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 501, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -13243,8 +14095,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:852 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" { ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 502, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -13263,8 +14116,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:853 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" { ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 503, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13278,8 +14132,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:854 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" { ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 503, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13293,8 +14148,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:855 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" { ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 504, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13308,8 +14164,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:856 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" { ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 504, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13323,8 +14180,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:857 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" { ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 505, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0, 0, @@ -13338,8 +14196,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:858 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" { ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 506, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13353,8 +14212,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:859 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" { ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 506, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13368,8 +14228,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:860 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" { ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 507, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -13386,8 +14247,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:861 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" { ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 508, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, + 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -13404,8 +14266,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:862 Instruction:"PCOMMIT" Encoding:"0x66 0x0F 0xAE /7:reg"/"" { ND_INS_PCOMMIT, ND_CAT_MISC, ND_SET_PCOMMIT, 509, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCOMMIT, 0, 0, 0, @@ -13418,8 +14281,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:863 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" { ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 510, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 0, 0, 0, @@ -13435,8 +14299,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:864 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" { ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 511, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -13451,8 +14316,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:865 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" { ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 512, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -13467,8 +14333,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:866 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" { ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 513, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13483,8 +14350,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:867 Instruction:"PEXTRB Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" { ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 513, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13499,8 +14367,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:868 Instruction:"PEXTRD Ey,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r ib"/"MRI" { ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 514, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13515,8 +14384,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:869 Instruction:"PEXTRQ Ey,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r ib"/"MRI" { ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 515, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13531,8 +14401,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:870 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" { ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 516, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -13547,8 +14418,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:871 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" { ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 516, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -13563,8 +14435,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:872 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" { ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 516, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13579,8 +14452,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:873 Instruction:"PEXTRW Rd,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" { ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 516, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -13595,8 +14469,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:874 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" { ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 517, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13610,8 +14485,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:875 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" { ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 518, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13625,8 +14501,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:876 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" { ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 519, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13640,8 +14517,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:877 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" { ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 520, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13655,8 +14533,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:878 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" { ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 521, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13670,8 +14549,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:879 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" { ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 522, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13685,8 +14565,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:880 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" { ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 523, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13700,8 +14581,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:881 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" { ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 524, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13715,8 +14597,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:882 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" { ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 525, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13730,8 +14613,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:883 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" { ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 526, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13745,8 +14629,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:884 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" { ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 527, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13760,8 +14645,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:885 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" { ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 528, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13775,8 +14661,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:886 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" { ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 529, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13790,8 +14677,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:887 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" { ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 530, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13805,8 +14693,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:888 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" { ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 531, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13820,8 +14709,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:889 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" { ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 532, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13835,8 +14725,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:890 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" { ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 533, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13850,8 +14741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:891 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" { ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 534, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13865,8 +14757,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:892 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" { ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 535, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13880,8 +14773,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:893 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" { ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 536, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13895,8 +14789,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:894 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" { ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 537, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -13910,8 +14805,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:895 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" { ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 538, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -13925,8 +14821,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:896 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" { ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 538, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -13940,8 +14837,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:897 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" { ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 539, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -13955,8 +14853,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:898 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" { ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 539, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -13970,8 +14869,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:899 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" { ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 540, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -13985,8 +14885,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:900 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" { ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 540, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -14000,8 +14901,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:901 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" { ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 541, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14015,8 +14917,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:902 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" { ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 542, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -14030,8 +14933,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:903 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" { ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 542, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -14045,8 +14949,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:904 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" { ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 543, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -14060,8 +14965,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:905 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" { ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 543, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -14075,8 +14981,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:906 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" { ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 544, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -14090,8 +14997,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:907 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" { ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 544, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -14105,8 +15013,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:908 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" { ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 545, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -14120,8 +15029,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:909 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" { ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 546, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -14135,8 +15045,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:910 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" { ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 547, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14151,8 +15062,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:911 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" { ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 547, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14167,8 +15079,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:912 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 548, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14183,8 +15096,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:913 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 549, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14199,8 +15113,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:914 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" { ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 550, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14215,8 +15130,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:915 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" { ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 550, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14231,8 +15147,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:916 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" { ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 550, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14247,8 +15164,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:917 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" { ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 550, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14263,8 +15181,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:918 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" { ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 551, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -14278,8 +15197,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:919 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" { ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 551, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -14293,8 +15213,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:920 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" { ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 552, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14308,8 +15229,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:921 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" { ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 552, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14323,8 +15245,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:922 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" { ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 553, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14338,8 +15261,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:923 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" { ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 554, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14353,8 +15277,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:924 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" { ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 555, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14368,8 +15293,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:925 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" { ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 555, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14383,8 +15309,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:926 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" { ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 556, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14398,8 +15325,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:927 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" { ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 556, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14413,8 +15341,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:928 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" { ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 557, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14428,8 +15357,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:929 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" { ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 558, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14443,8 +15373,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:930 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" { ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 559, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14458,8 +15389,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:931 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" { ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 560, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14473,8 +15405,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:932 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" { ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 561, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14488,8 +15421,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:933 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" { ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 561, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14503,8 +15437,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:934 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" { ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 562, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14518,8 +15453,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:935 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" { ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 562, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14533,8 +15469,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:936 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" { ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 563, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14548,8 +15485,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:937 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" { ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 564, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14563,8 +15501,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:938 Instruction:"PMOVMSKB Gd,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" { ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 565, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -14578,8 +15517,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:939 Instruction:"PMOVMSKB Gd,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" { ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 565, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14593,8 +15533,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:940 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" { ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 566, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14608,8 +15549,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:941 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" { ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 567, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14623,8 +15565,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:942 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" { ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 568, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14638,8 +15581,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:943 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" { ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 569, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14653,8 +15597,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:944 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" { ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 570, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14668,8 +15613,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:945 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" { ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 571, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14683,8 +15629,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:946 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" { ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 572, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14698,8 +15645,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:947 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" { ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 573, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14713,8 +15661,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:948 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" { ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 574, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14728,8 +15677,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:949 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" { ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 575, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14743,8 +15693,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:950 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" { ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 576, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14758,8 +15709,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:951 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" { ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 577, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14773,8 +15725,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:952 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" { ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 578, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14788,8 +15741,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:953 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" { ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 579, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -14803,8 +15757,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:954 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" { ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 579, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -14818,8 +15773,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:955 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" { ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 580, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -14833,8 +15789,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:956 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" { ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 581, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14848,8 +15805,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:957 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" { ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 581, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14863,8 +15821,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:958 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" { ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 582, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14878,8 +15837,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:959 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" { ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 582, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14893,8 +15853,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:960 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" { ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 583, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -14908,8 +15869,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:961 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" { ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 584, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -14923,8 +15885,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:962 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" { ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 584, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14938,8 +15901,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:963 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" { ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 585, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -14953,8 +15917,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:964 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" { ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 585, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -14968,8 +15933,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:965 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -14983,8 +15949,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:966 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -14998,8 +15965,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:967 Instruction:"POP ES" Encoding:"0x07"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -15013,8 +15981,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:968 Instruction:"POP SS" Encoding:"0x17"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -15028,8 +15997,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:969 Instruction:"POP DS" Encoding:"0x1F"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -15043,8 +16013,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:970 Instruction:"POP Zv" Encoding:"0x58"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15058,8 +16029,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:971 Instruction:"POP Zv" Encoding:"0x59"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15073,8 +16045,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:972 Instruction:"POP Zv" Encoding:"0x5A"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15088,8 +16061,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:973 Instruction:"POP Zv" Encoding:"0x5B"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15103,8 +16077,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:974 Instruction:"POP Zv" Encoding:"0x5C"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15118,8 +16093,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:975 Instruction:"POP Zv" Encoding:"0x5D"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15133,8 +16109,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:976 Instruction:"POP Zv" Encoding:"0x5E"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15148,8 +16125,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:977 Instruction:"POP Zv" Encoding:"0x5F"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15163,8 +16141,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:978 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 586, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15178,8 +16157,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:979 Instruction:"POPA" Encoding:"ds16 0x61"/"" { ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 587, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -15193,8 +16173,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:980 Instruction:"POPAD" Encoding:"ds32 0x61"/"" { ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 588, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -15208,8 +16189,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:981 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" { ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 589, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 0, 0|NDR_RFLAG_ZF, 0, @@ -15224,8 +16206,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:982 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" { ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 590, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15239,8 +16222,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:983 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" { ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 591, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15254,8 +16238,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:984 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" { ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 592, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -15269,8 +16254,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:985 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" { ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 593, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15284,8 +16270,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:986 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" { ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 593, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15299,8 +16286,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:987 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15313,8 +16301,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:988 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15327,8 +16316,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:989 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15341,8 +16331,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:990 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 594, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15355,8 +16346,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:991 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" { ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 595, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15369,8 +16361,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:992 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" { ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 596, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15383,8 +16376,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:993 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" { ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 597, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -15397,8 +16391,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:994 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" { ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 598, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -15411,8 +16406,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:995 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" { ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 599, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -15425,8 +16421,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:996 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" { ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 600, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -15439,8 +16436,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:997 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" { ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 601, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15453,8 +16451,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:998 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" { ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 602, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -15467,8 +16466,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:999 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" { ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 603, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15482,8 +16482,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1000 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" { ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 603, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15497,8 +16498,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1001 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" { ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 604, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -15512,8 +16514,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1002 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" { ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 604, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -15527,8 +16530,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1003 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 605, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15543,8 +16547,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1004 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 606, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15559,8 +16564,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1005 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 607, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15575,8 +16581,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1006 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 608, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15591,8 +16598,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1007 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" { ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 609, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -15606,8 +16614,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1008 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" { ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 609, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -15621,8 +16630,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1009 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" { ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 610, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -15636,8 +16646,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1010 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" { ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 610, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -15651,8 +16662,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1011 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" { ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 611, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, @@ -15666,8 +16678,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1012 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" { ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 611, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, @@ -15681,8 +16694,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1013 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" { ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 612, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15696,8 +16710,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1014 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" { ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 612, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15711,8 +16726,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1015 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" { ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 612, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15726,8 +16742,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1016 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" { ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 612, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15741,8 +16758,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1017 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" { ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 613, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15756,8 +16774,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1018 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" { ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 614, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15771,8 +16790,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1019 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" { ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 614, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15786,8 +16806,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1020 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" { ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 614, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15801,8 +16822,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1021 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" { ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 614, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15816,8 +16838,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1022 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" { ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 615, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15831,8 +16854,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1023 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" { ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 615, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15846,8 +16870,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1024 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" { ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 615, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15861,8 +16886,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1025 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" { ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 615, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15876,8 +16902,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1026 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" { ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 616, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, @@ -15891,8 +16918,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1027 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" { ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 617, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15906,8 +16934,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1028 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" { ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 617, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15921,8 +16950,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1029 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" { ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 617, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15936,8 +16966,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1030 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" { ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 617, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15951,8 +16982,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1031 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" { ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 618, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15966,8 +16998,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1032 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" { ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 618, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -15981,8 +17014,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1033 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" { ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 618, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -15996,8 +17030,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1034 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" { ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 618, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16011,8 +17046,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1035 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" { ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 619, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16026,8 +17062,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1036 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" { ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 619, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16041,8 +17078,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1037 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" { ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 619, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16056,8 +17094,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1038 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" { ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 619, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16071,8 +17110,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1039 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" { ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 620, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16086,8 +17126,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1040 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" { ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 621, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16101,8 +17142,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1041 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" { ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 621, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16116,8 +17158,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1042 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" { ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 621, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16131,8 +17174,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1043 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" { ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 621, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16146,8 +17190,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1044 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" { ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 622, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16161,8 +17206,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1045 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" { ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 622, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16176,8 +17222,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1046 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" { ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 622, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16191,8 +17238,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1047 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" { ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 622, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16206,8 +17254,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1048 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" { ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 623, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16221,8 +17270,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1049 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" { ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 623, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16236,8 +17286,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1050 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" { ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 624, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16251,8 +17302,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1051 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" { ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 624, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16266,8 +17318,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1052 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" { ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 625, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16281,8 +17334,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1053 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" { ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 625, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16296,8 +17350,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1054 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" { ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 626, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16311,8 +17366,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1055 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" { ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 626, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16326,8 +17382,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1056 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" { ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 627, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16341,8 +17398,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1057 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" { ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 627, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16356,8 +17414,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1058 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" { ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 628, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16371,8 +17430,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1059 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" { ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 628, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16386,8 +17446,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1060 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" { ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 629, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16401,8 +17462,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1061 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" { ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 629, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16416,8 +17478,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1062 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" { ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 630, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16431,8 +17494,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1063 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" { ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 630, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16446,8 +17510,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1064 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" { ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 631, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, @@ -16461,8 +17526,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1065 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" { ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 632, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, @@ -16477,8 +17543,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1066 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" { ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 633, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, 0, 0, 0, @@ -16491,8 +17558,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1067 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" { ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 634, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16506,8 +17574,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1068 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" { ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 634, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16521,8 +17590,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1069 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" { ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 635, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16536,8 +17606,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1070 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" { ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 635, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16551,8 +17622,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1071 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" { ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 636, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16566,8 +17638,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1072 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" { ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 637, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16581,8 +17654,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1073 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" { ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 637, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16596,8 +17670,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1074 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" { ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 638, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16611,8 +17686,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1075 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" { ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 638, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16626,8 +17702,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1076 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" { ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 639, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16641,8 +17718,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1077 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" { ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 639, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16656,8 +17734,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1078 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" { ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 640, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16671,8 +17750,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1079 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" { ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 641, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -16686,8 +17766,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1080 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" { ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 641, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -16701,8 +17782,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1081 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16716,8 +17798,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1082 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16731,8 +17814,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1083 Instruction:"PUSH ES" Encoding:"0x06"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -16746,8 +17830,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1084 Instruction:"PUSH CS" Encoding:"0x0E"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -16761,8 +17846,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1085 Instruction:"PUSH SS" Encoding:"0x16"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -16776,8 +17862,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1086 Instruction:"PUSH DS" Encoding:"0x1E"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -16791,8 +17878,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1087 Instruction:"PUSH Zv" Encoding:"0x50"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16806,8 +17894,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1088 Instruction:"PUSH Zv" Encoding:"0x51"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16821,8 +17910,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1089 Instruction:"PUSH Zv" Encoding:"0x52"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16836,8 +17926,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1090 Instruction:"PUSH Zv" Encoding:"0x53"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16851,8 +17942,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1091 Instruction:"PUSH Zv" Encoding:"0x54"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16866,8 +17958,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1092 Instruction:"PUSH Zv" Encoding:"0x55"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16881,8 +17974,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1093 Instruction:"PUSH Zv" Encoding:"0x56"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16896,8 +17990,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1094 Instruction:"PUSH Zv" Encoding:"0x57"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16911,8 +18006,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1095 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16926,8 +18022,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1096 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -16941,8 +18038,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1097 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 642, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 0, 0, 0, @@ -16956,8 +18054,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1098 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" { ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 643, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -16971,8 +18070,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1099 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" { ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 644, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, @@ -16986,8 +18086,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1100 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" { ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 645, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -17001,8 +18102,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1101 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" { ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 646, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -17016,8 +18118,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1102 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" { ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 647, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, @@ -17031,8 +18134,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1103 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" { ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 648, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF, 0, @@ -17048,8 +18152,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1104 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" { ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 649, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, @@ -17063,8 +18168,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1105 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" { ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 649, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -17078,8 +18184,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1106 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17094,8 +18201,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1107 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17110,8 +18218,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1108 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17126,8 +18235,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1109 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17142,8 +18252,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1110 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17158,8 +18269,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1111 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 650, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17174,8 +18286,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1112 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" { ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 651, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -17189,8 +18302,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1113 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" { ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 652, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -17204,8 +18318,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1114 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17220,8 +18335,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1115 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17236,8 +18352,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1116 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17252,8 +18369,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1117 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17268,8 +18386,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1118 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17284,8 +18403,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1119 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 653, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17300,8 +18420,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1120 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" { ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 654, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 0, 0, 0, @@ -17315,8 +18436,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1121 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" { ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 655, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 0, 0, 0, @@ -17330,8 +18452,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1122 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" { ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 656, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, 0, 0, 0, @@ -17347,8 +18470,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1123 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" { ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 657, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, 0, 0, 0, @@ -17362,8 +18486,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1124 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" { ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 658, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 0, 0, 0, @@ -17379,8 +18504,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1125 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" { ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 659, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -17396,8 +18522,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1126 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" { ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 660, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 0, 0|NDR_RFLAG_CF, 0, @@ -17413,8 +18540,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1127 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" { ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 661, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 0, 0|NDR_RFLAG_CF, 0, @@ -17428,8 +18556,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1128 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" { ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 661, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 0, 0|NDR_RFLAG_CF, 0, @@ -17443,8 +18572,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1129 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" { ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 662, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 0, 0|NDR_RFLAG_CF, 0, @@ -17458,8 +18588,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1130 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" { ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 662, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 0, 0|NDR_RFLAG_CF, 0, @@ -17473,8 +18604,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1131 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" { ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 663, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -17487,8 +18619,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1132 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" { ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 664, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, @@ -17502,8 +18635,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1133 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" { ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 665, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, @@ -17517,8 +18651,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1134 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" { ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 666, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -17533,8 +18668,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1135 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" { ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 667, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, 0, 0, 0, @@ -17551,8 +18687,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1136 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" { ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 668, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -17569,8 +18706,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1137 Instruction:"RETF" Encoding:"0xCB"/"" { ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 668, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -17586,8 +18724,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1138 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" { ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 669, + ND_PREF_BND, ND_MOD_ANY, - ND_PREF_BND, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -17604,8 +18743,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1139 Instruction:"RETN" Encoding:"0xC3"/"" { ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 669, + ND_PREF_BND, ND_MOD_ANY, - ND_PREF_BND, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, @@ -17620,8 +18760,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1140 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" { ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 670, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, @@ -17637,8 +18778,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1141 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" { ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 671, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, @@ -17653,8 +18795,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1142 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17669,8 +18812,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1143 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17685,8 +18829,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1144 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17701,8 +18846,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1145 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17717,8 +18863,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1146 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17733,8 +18880,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1147 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 672, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17749,8 +18897,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1148 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17765,8 +18914,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1149 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17781,8 +18931,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1150 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17797,8 +18948,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1151 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17813,8 +18965,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1152 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17829,8 +18982,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1153 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 673, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, @@ -17845,8 +18999,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1154 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 674, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -17861,8 +19016,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1155 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 675, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -17877,8 +19033,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1156 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" { ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 676, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -17893,8 +19050,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1157 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 677, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -17909,8 +19067,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1158 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 678, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, @@ -17925,8 +19084,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1159 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" { ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 679, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -17940,8 +19100,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1160 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" { ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 680, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -17954,8 +19115,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1161 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 681, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, @@ -17970,8 +19132,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1162 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 682, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -17985,8 +19148,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1163 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 683, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -18000,8 +19164,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1164 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 684, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0|NDR_RFLAG_CF, 0, @@ -18015,8 +19180,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1165 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" { ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 685, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -18029,8 +19195,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1166 Instruction:"SAHF" Encoding:"0x9E"/"" { ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 686, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0, @@ -18044,8 +19211,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1167 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18060,8 +19228,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1168 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18076,8 +19245,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1169 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18092,8 +19262,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1170 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18108,8 +19279,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1171 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18124,8 +19296,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1172 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 687, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18140,8 +19313,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1173 Instruction:"SALC" Encoding:"0xD6"/"" { ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 688, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -18155,8 +19329,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1174 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18171,8 +19346,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1175 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18187,8 +19363,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1176 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18203,8 +19380,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1177 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18219,8 +19397,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1178 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18235,8 +19414,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1179 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 689, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -18251,8 +19431,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1180 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 690, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -18267,8 +19448,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1181 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 691, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0|NDR_RFLAG_CF, 0, 0, @@ -18282,8 +19464,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1182 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18298,8 +19481,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1183 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18314,8 +19498,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1184 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18330,8 +19515,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1185 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18346,8 +19532,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1186 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18362,8 +19549,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1187 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18378,8 +19566,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1188 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18394,8 +19583,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1189 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18410,8 +19600,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1190 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + ND_PREF_HLE|ND_PREF_LOCK, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18426,8 +19617,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1191 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 692, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18442,8 +19634,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1192 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18459,8 +19652,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1193 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 693, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18477,8 +19671,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1194 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18494,8 +19689,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1195 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 694, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18512,8 +19708,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1196 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18529,8 +19726,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1197 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 695, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18547,8 +19745,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1198 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18564,8 +19763,9 @@ const ND_INSTRUCTION gInstructions[2561] = // Pos:1199 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 696, + ND_PREF_REPC, ND_MOD_ANY, - ND_PREF_REPC, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -18579,11 +19779,61 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1200 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + // Pos:1200 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { - ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 697, + ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 697, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + 0, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + { + 0 + }, + }, + + // Pos:1201 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + { + ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 698, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0, + 0, + 0, + { + OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), + OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rR8, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + OP(ND_OPT_GPR_rR9, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1202 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + { + ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 699, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + 0, + 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + 0, + 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + { + 0 + }, + }, + + // Pos:1203 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + { + ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 700, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, 0, 0, 0, @@ -18593,11 +19843,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1201 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + // Pos:1204 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 698, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -18608,11 +19859,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1202 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + // Pos:1205 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 699, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -18623,11 +19875,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1203 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + // Pos:1206 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 700, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -18638,11 +19891,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1204 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + // Pos:1207 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 701, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -18653,11 +19907,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1205 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + // Pos:1208 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 702, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, @@ -18668,11 +19923,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1206 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + // Pos:1209 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 703, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, @@ -18683,11 +19939,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1207 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + // Pos:1210 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 704, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, @@ -18698,11 +19955,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1208 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + // Pos:1211 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 705, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, @@ -18713,11 +19971,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1209 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + // Pos:1212 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 706, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 709, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_OF, 0, 0, @@ -18728,11 +19987,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1210 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + // Pos:1213 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 707, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -18743,11 +20003,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1211 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + // Pos:1214 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 708, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 711, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF, 0, 0, @@ -18758,11 +20019,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1212 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + // Pos:1215 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 709, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -18773,11 +20035,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1213 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + // Pos:1216 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 710, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 713, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_OF, 0, 0, @@ -18788,11 +20051,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1214 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + // Pos:1217 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 711, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, @@ -18803,11 +20067,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1215 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + // Pos:1218 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 712, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 715, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF, 0, 0, @@ -18818,11 +20083,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1216 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + // Pos:1219 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { - ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 713, + ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 716, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, @@ -18833,11 +20099,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1217 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + // Pos:1220 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 714, + ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 717, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, @@ -18848,11 +20115,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1218 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + // Pos:1221 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { - ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 715, + ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 718, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, @@ -18862,11 +20130,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1219 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + // Pos:1222 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { - ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 716, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 719, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -18877,11 +20146,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1220 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + // Pos:1223 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { - ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 717, + ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 720, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18892,11 +20162,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1221 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + // Pos:1224 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { - ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 718, + ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 721, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18907,11 +20178,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1222 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + // Pos:1225 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { - ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 719, + ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 722, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18922,11 +20194,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1223 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + // Pos:1226 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { - ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 720, + ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 723, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18938,11 +20211,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1224 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + // Pos:1227 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { - ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 721, + ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 724, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18953,11 +20227,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1225 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + // Pos:1228 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { - ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 722, + ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 725, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18968,11 +20243,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1226 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + // Pos:1229 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { - ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 723, + ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 726, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, @@ -18984,11 +20260,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1227 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + // Pos:1230 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19000,11 +20277,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1228 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + // Pos:1231 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19016,11 +20294,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1229 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + // Pos:1232 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19032,11 +20311,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1230 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + // Pos:1233 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19048,11 +20328,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1231 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + // Pos:1234 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19064,11 +20345,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1232 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + // Pos:1235 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 724, + ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 727, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19080,11 +20362,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1233 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + // Pos:1236 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 725, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 728, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -19097,11 +20380,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1234 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + // Pos:1237 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 725, + ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 728, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -19114,11 +20398,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1235 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1238 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 726, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 729, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -19130,11 +20415,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1236 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + // Pos:1239 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19146,11 +20432,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1237 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + // Pos:1240 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19162,11 +20449,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1238 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + // Pos:1241 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19178,11 +20466,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1239 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + // Pos:1242 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19194,11 +20483,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1240 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + // Pos:1243 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19210,11 +20500,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1241 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + // Pos:1244 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 727, + ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 730, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, @@ -19226,11 +20517,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1242 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + // Pos:1245 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 728, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 731, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -19243,11 +20535,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1243 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + // Pos:1246 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 728, + ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 731, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, @@ -19260,11 +20553,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1244 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + // Pos:1247 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { - ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 729, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, + ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 732, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, @@ -19276,11 +20570,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1245 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + // Pos:1248 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 730, + ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 733, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -19292,11 +20587,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1246 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + // Pos:1249 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { - ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 731, + ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 734, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -19308,11 +20604,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1247 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + // Pos:1250 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { - ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 732, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 735, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19323,11 +20620,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1248 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + // Pos:1251 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { - ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 733, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 736, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, @@ -19337,11 +20635,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1249 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + // Pos:1252 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 734, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 737, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19352,11 +20651,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1250 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + // Pos:1253 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 734, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 737, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19367,11 +20667,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1251 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + // Pos:1254 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { - ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 735, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, + ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 738, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, @@ -19381,11 +20682,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1252 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" + // Pos:1255 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" { - ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 736, + ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 739, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -19395,11 +20697,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1253 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + // Pos:1256 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 737, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 740, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19410,11 +20713,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1254 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + // Pos:1257 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 737, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 740, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19425,11 +20729,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1255 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + // Pos:1258 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { - ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 738, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 741, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19439,11 +20744,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1256 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + // Pos:1259 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 739, + ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 742, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -19454,11 +20760,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1257 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + // Pos:1260 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 740, + ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 743, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -19469,11 +20776,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1258 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + // Pos:1261 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 741, + ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 744, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -19484,11 +20792,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1259 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + // Pos:1262 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { - ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 742, + ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 745, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -19499,11 +20808,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1260 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + // Pos:1263 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { - ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 743, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, + ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 746, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 0, 0, 0|NDR_RFLAG_AC, @@ -19513,11 +20823,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1261 Instruction:"STC" Encoding:"0xF9"/"" + // Pos:1264 Instruction:"STC" Encoding:"0xF9"/"" { - ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 744, + ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 747, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, @@ -19527,11 +20838,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1262 Instruction:"STD" Encoding:"0xFD"/"" + // Pos:1265 Instruction:"STD" Encoding:"0xFD"/"" { - ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 745, + ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 748, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, @@ -19541,11 +20853,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1263 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + // Pos:1266 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { - ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 746, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, + ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 749, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, @@ -19555,11 +20868,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1264 Instruction:"STI" Encoding:"0xFB"/"" + // Pos:1267 Instruction:"STI" Encoding:"0xFB"/"" { - ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 747, + ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 750, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IF, @@ -19569,11 +20883,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1265 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + // Pos:1268 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { - ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 748, + ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 751, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, @@ -19584,11 +20899,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1266 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + // Pos:1269 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 749, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19601,11 +20917,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1267 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + // Pos:1270 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 749, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19619,11 +20936,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1268 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + // Pos:1271 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 750, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 753, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19636,11 +20954,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1269 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + // Pos:1272 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 750, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 753, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19654,11 +20973,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1270 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + // Pos:1273 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 751, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 754, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19671,11 +20991,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1271 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + // Pos:1274 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 751, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 754, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19689,11 +21010,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1272 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + // Pos:1275 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 755, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19706,11 +21028,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1273 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + // Pos:1276 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 752, + ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 755, + ND_PREF_REP, ND_MOD_ANY, - ND_PREF_REP, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, @@ -19724,11 +21047,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1274 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + // Pos:1277 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 753, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 756, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19739,11 +21063,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1275 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + // Pos:1278 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 753, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 756, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -19754,11 +21079,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1276 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + // Pos:1279 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { - ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 754, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 757, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -19768,11 +21094,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1277 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + // Pos:1280 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19784,11 +21111,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1278 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + // Pos:1281 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19800,11 +21128,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1279 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + // Pos:1282 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19816,11 +21145,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1280 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + // Pos:1283 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19832,11 +21162,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1281 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + // Pos:1284 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19848,11 +21179,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1282 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + // Pos:1285 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19864,11 +21196,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1283 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + // Pos:1286 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19880,11 +21213,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1284 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + // Pos:1287 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19896,11 +21230,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1285 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + // Pos:1288 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + ND_PREF_HLE|ND_PREF_LOCK, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19912,11 +21247,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1286 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + // Pos:1289 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 755, + ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 758, + ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, - ND_PREF_HLE|ND_PREF_LOCK, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, @@ -19928,11 +21264,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1287 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + // Pos:1290 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 756, + ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 759, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -19943,11 +21280,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1288 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + // Pos:1291 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { - ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 757, + ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 760, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -19958,11 +21296,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1289 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + // Pos:1292 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 758, + ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 761, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -19973,11 +21312,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1290 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + // Pos:1293 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { - ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 759, + ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 762, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -19988,11 +21328,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1291 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" + // Pos:1294 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" { - ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 760, + ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 763, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -20003,11 +21344,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1292 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" + // Pos:1295 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" { - ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 761, + ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 764, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -20017,11 +21359,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1293 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" + // Pos:1296 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" { - ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 762, + ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 765, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -20031,11 +21374,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1294 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + // Pos:1297 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { - ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 763, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, + ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 766, + 0, + ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0, 0, @@ -20046,11 +21390,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1295 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + // Pos:1298 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { - ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 764, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_FSC, + ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 767, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_FSC, 0, 0, 0, @@ -20069,11 +21414,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1296 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + // Pos:1299 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { - ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 765, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, + ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 768, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SEP, 0, 0, 0, @@ -20091,11 +21437,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1297 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + // Pos:1300 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { - ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 766, - ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, + ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 769, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, 0, 0, 0, @@ -20109,11 +21456,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1298 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + // Pos:1301 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { - ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 767, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, + ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 770, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, 0, 0, 0, @@ -20130,11 +21478,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1299 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + // Pos:1302 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { - ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 768, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 771, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -20145,11 +21494,27 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1300 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + // Pos:1303 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + { + ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 772, + 0, + ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, + 0, + 0, + 0, + { + 0 + }, + }, + + // Pos:1304 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { - ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 769, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, + ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 773, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, 0, 0, 0, @@ -20161,11 +21526,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1301 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + // Pos:1305 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 770, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 774, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, @@ -20177,11 +21543,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1302 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + // Pos:1306 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 771, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 775, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, @@ -20193,11 +21560,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1303 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + // Pos:1307 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 772, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 776, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, @@ -20209,11 +21577,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1304 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + // Pos:1308 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" { - ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 773, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, + ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 777, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, @@ -20225,11 +21594,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1305 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + // Pos:1309 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20241,11 +21611,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1306 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + // Pos:1310 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20257,11 +21628,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1307 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + // Pos:1311 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20273,11 +21645,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1308 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + // Pos:1312 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20289,11 +21662,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1309 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + // Pos:1313 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20305,11 +21679,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1310 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + // Pos:1314 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20321,11 +21696,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1311 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + // Pos:1315 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20337,11 +21713,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1312 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + // Pos:1316 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 774, + ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 778, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, @@ -20353,11 +21730,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1313 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1317 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 775, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 779, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -20368,11 +21746,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1314 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1318 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 776, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 780, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -20383,11 +21762,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1315 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + // Pos:1319 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { - ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 777, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 781, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -20397,11 +21777,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1316 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + // Pos:1320 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { - ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 778, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, + ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 782, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -20412,11 +21793,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1317 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + // Pos:1321 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { - ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 779, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, + ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 783, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, @@ -20426,11 +21808,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1318 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" + // Pos:1322 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" { - ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 780, - ND_MOD_R0|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, + ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 784, + 0, + ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 0, 0, 0, @@ -20440,11 +21823,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1319 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + // Pos:1323 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { - ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 781, + ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 785, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, 0|NDR_RFLAG_CF, 0, @@ -20457,11 +21841,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1320 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" + // Pos:1324 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" { - ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 782, + ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 786, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, @@ -20473,11 +21858,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1321 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + // Pos:1325 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { - ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 783, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, + ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 787, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, @@ -20488,11 +21874,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1322 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + // Pos:1326 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 784, + ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 788, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -20504,11 +21891,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1323 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + // Pos:1327 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { - ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 785, + ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 789, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -20520,11 +21908,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1324 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + // Pos:1328 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { - ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 786, + ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 790, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -20535,11 +21924,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1325 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + // Pos:1329 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" { - ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 787, + ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 791, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, @@ -20550,11 +21940,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1326 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + // Pos:1330 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { - ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 788, + ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 792, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, + 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -20564,11 +21955,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1327 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + // Pos:1331 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 789, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 793, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, 0|NDR_RFLAG_CF, 0, @@ -20579,11 +21971,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1328 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + // Pos:1332 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { - ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 790, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_SMM|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX, - 0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, + ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 794, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, 0, 0, @@ -20595,11 +21988,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1329 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + // Pos:1333 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 791, + ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 795, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -20610,11 +22004,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1330 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + // Pos:1334 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" { - ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 792, + ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 796, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -20625,11 +22020,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1331 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + // Pos:1335 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 793, + ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 797, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, @@ -20640,11 +22036,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1332 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + // Pos:1336 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { - ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 794, + ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 798, + 0, ND_MOD_ANY, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, @@ -20655,11 +22052,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1333 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + // Pos:1337 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { - ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 795, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 799, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, @@ -20672,11 +22070,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1334 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + // Pos:1338 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { - ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 796, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 800, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, @@ -20689,11 +22088,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1335 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + // Pos:1339 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { - ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 797, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 801, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, @@ -20706,11 +22106,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1336 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + // Pos:1340 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { - ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 798, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, + ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 802, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, @@ -20723,11 +22124,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1337 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + // Pos:1341 Instruction:"VADDPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { - ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 799, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 803, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -20740,11 +22142,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1338 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + // Pos:1342 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 799, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 803, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -20756,11 +22159,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1339 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + // Pos:1343 Instruction:"VADDPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { - ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 800, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 804, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -20773,11 +22177,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1340 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + // Pos:1344 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { - ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 800, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 804, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -20789,11 +22194,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1341 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + // Pos:1345 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { - ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 801, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 805, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -20806,11 +22212,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1342 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + // Pos:1346 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 801, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 805, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -20822,11 +22229,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1343 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + // Pos:1347 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { - ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 802, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 806, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -20839,11 +22247,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1344 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + // Pos:1348 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { - ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 802, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 806, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -20855,11 +22264,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1345 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + // Pos:1349 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 803, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 807, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -20871,11 +22281,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1346 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + // Pos:1350 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { - ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 804, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 808, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -20887,11 +22298,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1347 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1351 Instruction:"VAESDEC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 805, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 809, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, @@ -20903,11 +22315,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1348 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + // Pos:1352 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { - ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 805, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 809, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -20919,11 +22332,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1349 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1353 Instruction:"VAESDECLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 806, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 810, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, @@ -20935,11 +22349,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1350 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + // Pos:1354 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { - ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 806, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 810, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -20951,11 +22366,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1351 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1355 Instruction:"VAESENC Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 807, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 811, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, @@ -20967,11 +22383,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1352 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + // Pos:1356 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { - ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 807, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 811, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -20983,11 +22400,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1353 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1357 Instruction:"VAESENCLAST Vn,Hn,Wn" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 808, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, + ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 812, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, @@ -20999,11 +22417,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1354 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + // Pos:1358 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { - ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 808, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 812, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -21015,11 +22434,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1355 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + // Pos:1359 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" { - ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 809, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 813, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -21030,11 +22450,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1356 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + // Pos:1360 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" { - ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 810, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, + ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 814, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, @@ -21046,11 +22467,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1357 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + // Pos:1361 Instruction:"VALIGND Vn{K}{z},aKq,Hn,Wn|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 811, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 815, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21064,11 +22486,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1358 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + // Pos:1362 Instruction:"VALIGNQ Vn{K}{z},aKq,Hn,Wn|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { - ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 812, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 816, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21082,11 +22505,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1359 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + // Pos:1363 Instruction:"VANDNPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 813, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 817, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21099,11 +22523,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1360 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + // Pos:1364 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 813, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 817, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21115,11 +22540,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1361 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + // Pos:1365 Instruction:"VANDNPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 814, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 818, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21132,11 +22558,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1362 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + // Pos:1366 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 814, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 818, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21148,11 +22575,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1363 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + // Pos:1367 Instruction:"VANDPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 815, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 819, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21165,11 +22593,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1364 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + // Pos:1368 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 815, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 819, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21181,11 +22610,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1365 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + // Pos:1369 Instruction:"VANDPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 816, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 820, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21198,11 +22628,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1366 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + // Pos:1370 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 816, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 820, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21214,11 +22645,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1367 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + // Pos:1371 Instruction:"VBLENDMPD Vn{K}{z},aKq,Hn,Wn|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 817, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 821, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21231,11 +22663,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1368 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + // Pos:1372 Instruction:"VBLENDMPS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { - ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 818, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 822, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21248,11 +22681,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1369 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + // Pos:1373 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { - ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 819, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 823, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21265,11 +22699,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1370 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + // Pos:1374 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { - ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 820, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 824, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21282,11 +22717,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1371 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + // Pos:1375 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" { - ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 821, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 825, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21299,11 +22735,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1372 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + // Pos:1376 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" { - ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 822, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 826, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21316,11 +22753,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1373 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + // Pos:1377 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { - ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 823, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 827, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21331,11 +22769,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1374 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + // Pos:1378 Instruction:"VBROADCASTF32X2 Vu{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { - ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 824, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 828, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21347,11 +22786,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1375 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + // Pos:1379 Instruction:"VBROADCASTF32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 825, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 829, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21363,11 +22803,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1376 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + // Pos:1380 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 826, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 830, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21379,11 +22820,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1377 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + // Pos:1381 Instruction:"VBROADCASTF64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 827, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 831, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21395,11 +22837,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1378 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + // Pos:1382 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { - ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 828, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 832, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21411,11 +22854,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1379 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + // Pos:1383 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { - ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 829, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 833, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, @@ -21426,11 +22870,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1380 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + // Pos:1384 Instruction:"VBROADCASTI32X2 Vn{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { - ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 830, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 834, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21442,11 +22887,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1381 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + // Pos:1385 Instruction:"VBROADCASTI32X4 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 831, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 835, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21458,11 +22904,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1382 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + // Pos:1386 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 832, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 836, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21474,11 +22921,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1383 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + // Pos:1387 Instruction:"VBROADCASTI64X2 Vu{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 833, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 837, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -21490,11 +22938,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1384 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + // Pos:1388 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { - ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 834, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 838, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21506,11 +22955,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1385 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + // Pos:1389 Instruction:"VBROADCASTSD Vu{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 835, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 839, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21522,11 +22972,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1386 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + // Pos:1390 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 835, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 839, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21537,11 +22988,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1387 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + // Pos:1391 Instruction:"VBROADCASTSS Vn{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 836, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 840, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21553,11 +23005,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1388 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + // Pos:1392 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 836, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 840, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21568,11 +23021,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1389 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1393 Instruction:"VCMPPD rKq{K},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 837, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 841, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21586,11 +23040,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1390 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + // Pos:1394 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 837, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 841, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21603,11 +23058,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1391 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1395 Instruction:"VCMPPS rKq{K},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 838, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 842, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21621,11 +23077,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1392 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1396 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 838, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 842, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21638,11 +23095,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1393 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + // Pos:1397 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 839, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 843, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21656,11 +23114,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1394 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1398 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 839, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 843, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21673,11 +23132,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1395 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + // Pos:1399 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { - ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 840, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 844, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21691,11 +23151,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1396 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + // Pos:1400 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { - ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 840, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 844, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21708,11 +23169,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1397 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + // Pos:1401 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 841, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 845, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -21724,11 +23186,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1398 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + // Pos:1402 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 841, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 845, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -21740,11 +23203,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1399 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + // Pos:1403 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 842, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 846, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -21756,11 +23220,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1400 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + // Pos:1404 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { - ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 842, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 846, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, @@ -21772,11 +23237,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1401 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + // Pos:1405 Instruction:"VCOMPRESSPD Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 843, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 847, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21788,11 +23254,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1402 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + // Pos:1406 Instruction:"VCOMPRESSPS Wn{K}{z},aKq,Vn" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { - ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 844, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 848, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21804,11 +23271,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1403 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + // Pos:1407 Instruction:"VCVTDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 845, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 849, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21820,11 +23288,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1404 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + // Pos:1408 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 845, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 849, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21835,11 +23304,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1405 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + // Pos:1409 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 845, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 849, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21850,11 +23320,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1406 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + // Pos:1410 Instruction:"VCVTDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 846, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21866,11 +23337,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1407 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + // Pos:1411 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 846, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 850, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21881,11 +23353,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1408 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + // Pos:1412 Instruction:"VCVTNE2PS2BF16 Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { - ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 847, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 851, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 0, 0, 0, @@ -21898,11 +23371,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1409 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + // Pos:1413 Instruction:"VCVTNEPS2BF16 Vh{K}{z},aKq,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 848, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 852, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 0, 0, 0, @@ -21914,11 +23388,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1410 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + // Pos:1414 Instruction:"VCVTPD2DQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 849, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 853, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21930,11 +23405,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1411 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + // Pos:1415 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 849, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 853, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21945,11 +23421,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1412 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + // Pos:1416 Instruction:"VCVTPD2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 850, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 854, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -21961,11 +23438,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1413 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + // Pos:1417 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 850, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 854, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21976,11 +23454,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1414 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + // Pos:1418 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 850, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 854, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -21991,11 +23470,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1415 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + // Pos:1419 Instruction:"VCVTPD2QQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { - ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 851, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 855, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22007,11 +23487,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1416 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + // Pos:1420 Instruction:"VCVTPD2UDQ Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 852, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 856, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22023,11 +23504,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1417 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + // Pos:1421 Instruction:"VCVTPD2UQQ Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { - ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 853, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 857, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22039,11 +23521,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1418 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + // Pos:1422 Instruction:"VCVTPH2PS Vn{K}{z},aKq,Wh{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 854, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 858, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22055,11 +23538,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1419 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + // Pos:1423 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 854, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 858, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, @@ -22070,11 +23554,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1420 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + // Pos:1424 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 854, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 858, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, @@ -22085,11 +23570,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1421 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + // Pos:1425 Instruction:"VCVTPS2DQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 855, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 859, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22101,11 +23587,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1422 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + // Pos:1426 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 855, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 859, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22116,11 +23603,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1423 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + // Pos:1427 Instruction:"VCVTPS2PD Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 856, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 860, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22132,11 +23620,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1424 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + // Pos:1428 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 856, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22147,11 +23636,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1425 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + // Pos:1429 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 856, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 860, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22162,11 +23652,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1426 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + // Pos:1430 Instruction:"VCVTPS2PH Wh{K}{z},aKq,Vn{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 857, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 861, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22179,11 +23670,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1427 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + // Pos:1431 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 857, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 861, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, @@ -22195,11 +23687,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1428 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + // Pos:1432 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 857, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, + ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 861, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, @@ -22211,11 +23704,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1429 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + // Pos:1433 Instruction:"VCVTPS2QQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { - ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 858, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 862, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22227,11 +23721,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1430 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + // Pos:1434 Instruction:"VCVTPS2UDQ Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 859, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 863, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22243,11 +23738,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1431 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + // Pos:1435 Instruction:"VCVTPS2UQQ Vn{K}{z},aKq,Wh|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { - ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 860, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 864, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22259,11 +23755,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1432 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + // Pos:1436 Instruction:"VCVTQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 861, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 865, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22275,11 +23772,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1433 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + // Pos:1437 Instruction:"VCVTQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { - ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 862, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 866, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22291,11 +23789,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1434 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1438 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 863, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 867, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22306,11 +23805,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1435 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + // Pos:1439 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 863, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 867, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22321,11 +23821,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1436 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + // Pos:1440 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 864, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 868, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22338,11 +23839,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1437 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + // Pos:1441 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 864, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 868, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22354,11 +23856,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1438 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + // Pos:1442 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 865, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 869, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22369,11 +23872,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1439 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + // Pos:1443 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 866, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 870, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22385,11 +23889,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1440 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + // Pos:1444 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 866, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 870, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22401,11 +23906,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1441 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + // Pos:1445 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 866, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 870, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22417,11 +23923,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1442 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1446 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 867, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 871, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22433,11 +23940,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1443 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + // Pos:1447 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 867, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 871, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22449,11 +23957,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1444 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + // Pos:1448 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 868, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 872, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22466,11 +23975,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1445 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + // Pos:1449 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 868, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 872, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22482,11 +23992,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1446 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1450 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 869, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 873, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22497,11 +24008,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1447 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + // Pos:1451 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 869, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 873, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22512,11 +24024,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1448 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + // Pos:1452 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { - ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 870, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 874, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22527,11 +24040,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1449 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + // Pos:1453 Instruction:"VCVTTPD2DQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 871, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 875, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22543,11 +24057,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1450 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + // Pos:1454 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 871, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 875, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22558,11 +24073,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1451 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + // Pos:1455 Instruction:"VCVTTPD2QQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 872, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 876, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22574,11 +24090,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1452 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + // Pos:1456 Instruction:"VCVTTPD2UDQ Vh{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 873, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 877, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22590,11 +24107,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1453 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + // Pos:1457 Instruction:"VCVTTPD2UQQ Vn{K}{z},aKq,Wn|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { - ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 874, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 878, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22606,11 +24124,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1454 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + // Pos:1458 Instruction:"VCVTTPS2DQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 875, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 879, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22622,11 +24141,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1455 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + // Pos:1459 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 875, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 879, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22637,11 +24157,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1456 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + // Pos:1460 Instruction:"VCVTTPS2QQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 876, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 880, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22653,11 +24174,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1457 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + // Pos:1461 Instruction:"VCVTTPS2UDQ Vn{K}{z},aKq,Wn|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 877, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 881, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22669,11 +24191,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1458 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + // Pos:1462 Instruction:"VCVTTPS2UQQ Vn{K}{z},aKq,Wh|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { - ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 878, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 882, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22685,11 +24208,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1459 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1463 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 879, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 883, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22700,11 +24224,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1460 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + // Pos:1464 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 879, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 883, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22715,11 +24240,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1461 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + // Pos:1465 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 880, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 884, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22730,11 +24256,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1462 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1466 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 881, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 885, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22745,11 +24272,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1463 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + // Pos:1467 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 881, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 885, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22760,11 +24288,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1464 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + // Pos:1468 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { - ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 882, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 886, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22775,11 +24304,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1465 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + // Pos:1469 Instruction:"VCVTUDQ2PD Vn{K}{z},aKq,Wh|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 883, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22791,11 +24321,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1466 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + // Pos:1470 Instruction:"VCVTUDQ2PS Vn{K}{z},aKq,Wn|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { - ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 884, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 888, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22807,11 +24338,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1467 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + // Pos:1471 Instruction:"VCVTUQQ2PD Vn{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 885, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 889, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22823,11 +24355,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1468 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + // Pos:1472 Instruction:"VCVTUQQ2PS Vh{K}{z},aKq,Wn|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { - ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 886, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 890, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -22839,11 +24372,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1469 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + // Pos:1473 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 891, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22855,11 +24389,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1470 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + // Pos:1474 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 887, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 891, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22871,11 +24406,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1471 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + // Pos:1475 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { - ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 888, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 892, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22887,11 +24423,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1472 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + // Pos:1476 Instruction:"VDBPSADBW Vn{K}{z},aKq,Hn,Wn,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { - ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 889, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, + ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 893, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, @@ -22905,11 +24442,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1473 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + // Pos:1477 Instruction:"VDIVPD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 890, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 894, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22922,11 +24460,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1474 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + // Pos:1478 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 890, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 894, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22938,11 +24477,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1475 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + // Pos:1479 Instruction:"VDIVPS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 891, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 895, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22955,11 +24495,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1476 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + // Pos:1480 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { - ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 891, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 895, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -22971,11 +24512,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1477 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + // Pos:1481 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { - ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 892, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 896, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -22988,11 +24530,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1478 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + // Pos:1482 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 892, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 896, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23004,11 +24547,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1479 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + // Pos:1483 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { - ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 893, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 897, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23021,11 +24565,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1480 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + // Pos:1484 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { - ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 893, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 897, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23037,11 +24582,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1481 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + // Pos:1485 Instruction:"VDPBF16PS Vn{K}{z},aKq,Hn,Wn|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { - ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 894, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, + ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 898, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 0, 0, 0, @@ -23054,11 +24600,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1482 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + // Pos:1486 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { - ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 895, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 899, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23071,11 +24618,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1483 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + // Pos:1487 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { - ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 896, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 900, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23088,11 +24636,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1484 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + // Pos:1488 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { - ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 897, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 901, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -23103,11 +24652,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1485 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + // Pos:1489 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { - ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 898, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_SMM|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO|ND_MOD_SGX|ND_MOD_TSX, - 0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, + ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 902, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, @@ -23118,11 +24668,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1486 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + // Pos:1490 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { - ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 899, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 903, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, @@ -23134,11 +24685,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1487 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + // Pos:1491 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { - ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 900, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, + ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 904, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, @@ -23150,11 +24702,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1488 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + // Pos:1492 Instruction:"VEXPANDPD Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { - ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 901, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 905, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23166,11 +24719,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1489 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + // Pos:1493 Instruction:"VEXPANDPS Vn{K}{z},aKq,Wn" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { - ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 902, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 906, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23182,11 +24736,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1490 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + // Pos:1494 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { - ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 903, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 907, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23198,11 +24753,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1491 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + // Pos:1495 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 904, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 908, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23215,11 +24771,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1492 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + // Pos:1496 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 905, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 909, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -23232,11 +24789,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1493 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + // Pos:1497 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { - ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 906, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 910, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -23249,11 +24807,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1494 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + // Pos:1498 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { - ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 907, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 911, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23266,11 +24825,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1495 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + // Pos:1499 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { - ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 908, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, + ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 912, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, @@ -23282,11 +24842,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1496 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + // Pos:1500 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 909, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 913, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23299,11 +24860,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1497 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + // Pos:1501 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 910, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 914, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -23316,11 +24878,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1498 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + // Pos:1502 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vu,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { - ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 911, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, + ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 915, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, @@ -23333,11 +24896,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1499 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + // Pos:1503 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { - ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 912, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 916, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23350,11 +24914,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1500 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1504 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 913, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 917, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23366,11 +24931,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1501 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1505 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 913, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 917, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23382,11 +24948,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1502 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + // Pos:1506 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 913, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 917, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23398,11 +24965,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1503 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + // Pos:1507 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 913, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, + ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 917, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, @@ -23414,11 +24982,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1504 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + // Pos:1508 Instruction:"VFIXUPIMMPD Vn{K}{z},aKq,Hn,Wn|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 914, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 918, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23432,11 +25001,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1505 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + // Pos:1509 Instruction:"VFIXUPIMMPS Vn{K}{z},aKq,Hn,Wn|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 915, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 919, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23450,11 +25020,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1506 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + // Pos:1510 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 916, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 920, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23468,11 +25039,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1507 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + // Pos:1511 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { - ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 917, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 921, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23486,11 +25058,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1508 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + // Pos:1512 Instruction:"VFMADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 918, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 922, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23503,11 +25076,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1509 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + // Pos:1513 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 918, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 922, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23519,11 +25093,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1510 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + // Pos:1514 Instruction:"VFMADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 919, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 923, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23536,11 +25111,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1511 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + // Pos:1515 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 919, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 923, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23552,11 +25128,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1512 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + // Pos:1516 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 920, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 924, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23569,11 +25146,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1513 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + // Pos:1517 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 920, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 924, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23585,11 +25163,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1514 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + // Pos:1518 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 921, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 925, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23602,11 +25181,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1515 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + // Pos:1519 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 921, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 925, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23618,11 +25198,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1516 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + // Pos:1520 Instruction:"VFMADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 922, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 926, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23635,11 +25216,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1517 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + // Pos:1521 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 922, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 926, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23651,11 +25233,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1518 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + // Pos:1522 Instruction:"VFMADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 923, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 927, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23668,11 +25251,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1519 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + // Pos:1523 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 923, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 927, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23684,11 +25268,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1520 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + // Pos:1524 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 924, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 928, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23701,11 +25286,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1521 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + // Pos:1525 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 924, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 928, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23717,11 +25303,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1522 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + // Pos:1526 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 925, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 929, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23734,11 +25321,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1523 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + // Pos:1527 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 925, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 929, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23750,11 +25338,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1524 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + // Pos:1528 Instruction:"VFMADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 926, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 930, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23767,11 +25356,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1525 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + // Pos:1529 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 926, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 930, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23783,11 +25373,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1526 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + // Pos:1530 Instruction:"VFMADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 927, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 931, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23800,11 +25391,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1527 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + // Pos:1531 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 927, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 931, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23816,11 +25408,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1528 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + // Pos:1532 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 928, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 932, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23833,11 +25426,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1529 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + // Pos:1533 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 928, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 932, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23849,11 +25443,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1530 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + // Pos:1534 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 929, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 933, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -23866,11 +25461,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1531 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + // Pos:1535 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 929, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 933, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -23882,11 +25478,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1532 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + // Pos:1536 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 930, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 934, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -23899,11 +25496,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1533 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + // Pos:1537 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 930, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 934, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -23916,11 +25514,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1534 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + // Pos:1538 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 931, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 935, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -23933,11 +25532,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1535 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + // Pos:1539 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 931, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 935, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -23950,11 +25550,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1536 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + // Pos:1540 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 932, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 936, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -23967,11 +25568,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1537 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + // Pos:1541 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 932, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 936, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -23984,11 +25586,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1538 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + // Pos:1542 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 933, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 937, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24001,11 +25604,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1539 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + // Pos:1543 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 933, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 937, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24018,11 +25622,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1540 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + // Pos:1544 Instruction:"VFMADDSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 934, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 938, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24035,11 +25640,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1541 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + // Pos:1545 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 934, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 938, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24051,11 +25657,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1542 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + // Pos:1546 Instruction:"VFMADDSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 935, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 939, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24068,11 +25675,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1543 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + // Pos:1547 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 935, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 939, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24084,11 +25692,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1544 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + // Pos:1548 Instruction:"VFMADDSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 936, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 940, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24101,11 +25710,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1545 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + // Pos:1549 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 936, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 940, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24117,11 +25727,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1546 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + // Pos:1550 Instruction:"VFMADDSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 937, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 941, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24134,11 +25745,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1547 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + // Pos:1551 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 937, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 941, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24150,11 +25762,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1548 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + // Pos:1552 Instruction:"VFMADDSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 938, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 942, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24167,11 +25780,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1549 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + // Pos:1553 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 938, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 942, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24183,11 +25797,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1550 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + // Pos:1554 Instruction:"VFMADDSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 939, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 943, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24200,11 +25815,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1551 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + // Pos:1555 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 939, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 943, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24216,11 +25832,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1552 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + // Pos:1556 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 940, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 944, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24233,11 +25850,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1553 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + // Pos:1557 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 940, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 944, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24250,11 +25868,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1554 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + // Pos:1558 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 941, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 945, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24267,11 +25886,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1555 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + // Pos:1559 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 941, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 945, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24284,11 +25904,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1556 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + // Pos:1560 Instruction:"VFMSUB132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 942, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 946, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24301,11 +25922,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1557 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + // Pos:1561 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 942, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 946, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24317,11 +25939,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1558 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + // Pos:1562 Instruction:"VFMSUB132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 943, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 947, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24334,11 +25957,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1559 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + // Pos:1563 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 943, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 947, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24350,11 +25974,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1560 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + // Pos:1564 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 944, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 948, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24367,11 +25992,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1561 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + // Pos:1565 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 944, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 948, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24383,11 +26009,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1562 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + // Pos:1566 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 945, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 949, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24400,11 +26027,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1563 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + // Pos:1567 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 945, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 949, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24416,11 +26044,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1564 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + // Pos:1568 Instruction:"VFMSUB213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 946, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 950, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24433,11 +26062,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1565 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + // Pos:1569 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 946, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 950, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24449,11 +26079,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1566 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + // Pos:1570 Instruction:"VFMSUB213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 947, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 951, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24466,11 +26097,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1567 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + // Pos:1571 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 947, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 951, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24482,11 +26114,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1568 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + // Pos:1572 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 948, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 952, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24499,11 +26132,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1569 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + // Pos:1573 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 948, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 952, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24515,11 +26149,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1570 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + // Pos:1574 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 949, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 953, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24532,11 +26167,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1571 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + // Pos:1575 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 949, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 953, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24548,11 +26184,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1572 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + // Pos:1576 Instruction:"VFMSUB231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 950, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 954, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24565,11 +26202,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1573 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + // Pos:1577 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 950, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 954, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24581,11 +26219,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1574 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + // Pos:1578 Instruction:"VFMSUB231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 951, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 955, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24598,11 +26237,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1575 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + // Pos:1579 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 951, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 955, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24614,11 +26254,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1576 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + // Pos:1580 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 952, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 956, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24631,11 +26272,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1577 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + // Pos:1581 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 952, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 956, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24647,11 +26289,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1578 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + // Pos:1582 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 953, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 957, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24664,11 +26307,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1579 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + // Pos:1583 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 953, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 957, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24680,11 +26324,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1580 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + // Pos:1584 Instruction:"VFMSUBADD132PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 954, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 958, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24697,11 +26342,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1581 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + // Pos:1585 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 954, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 958, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24713,11 +26359,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1582 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + // Pos:1586 Instruction:"VFMSUBADD132PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 955, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 959, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24730,11 +26377,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1583 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + // Pos:1587 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 955, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 959, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24746,11 +26394,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1584 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + // Pos:1588 Instruction:"VFMSUBADD213PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 956, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 960, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24763,11 +26412,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1585 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + // Pos:1589 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 956, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 960, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24779,11 +26429,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1586 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + // Pos:1590 Instruction:"VFMSUBADD213PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 957, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 961, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24796,11 +26447,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1587 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + // Pos:1591 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 957, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 961, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24812,11 +26464,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1588 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + // Pos:1592 Instruction:"VFMSUBADD231PD Vn{K}{z},aKq,Hn,Wn|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 958, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 962, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24829,11 +26482,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1589 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + // Pos:1593 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 958, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 962, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24845,11 +26499,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1590 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + // Pos:1594 Instruction:"VFMSUBADD231PS Vn{K}{z},aKq,Hn,Wn|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 959, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 963, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, @@ -24862,11 +26517,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1591 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + // Pos:1595 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 959, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, + ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 963, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, @@ -24878,11 +26534,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1592 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + // Pos:1596 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 960, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 964, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24895,11 +26552,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1593 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + // Pos:1597 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 960, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 964, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24912,11 +26570,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1594 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + // Pos:1598 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 961, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 965, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24929,11 +26588,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1595 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + // Pos:1599 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 961, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 965, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24946,11 +26606,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1596 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + // Pos:1600 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 962, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 966, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24963,11 +26624,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1597 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + // Pos:1601 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 962, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 966, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24980,11 +26642,12 @@ const ND_INSTRUCTION gInstructions[2561] = }, }, - // Pos:1598 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + // Pos:1602 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 963, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_TSX|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXO, - 0, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, + ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 967, + 0, + ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, @@ -24997,11 +26660,12 @@ const ND_INSTRUCTION gInstructions[2561]