mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-11-21 23:18:09 +00:00
Some more type cast warnings fixed.
This commit is contained in:
parent
f1a85df2e7
commit
270587903e
@ -250,24 +250,7 @@ ShemuCopyMem(
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ND_UINT64 Size
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ND_UINT64 Size
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)
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)
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{
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{
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switch (Size)
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shemu_memcpy(Destination, Source, (ND_SIZET)Size);
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{
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case 1:
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*Destination = *Source;
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break;
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case 2:
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*(ND_UINT16 *)Destination = *(ND_UINT16 *)Source;
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break;
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case 4:
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*(ND_UINT32 *)Destination = *(ND_UINT32 *)Source;
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break;
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case 8:
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*(ND_UINT64 *)Destination = *(ND_UINT64 *)Source;
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break;
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default:
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shemu_memcpy(Destination, Source, (ND_SIZET)Size);
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break;
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}
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}
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}
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@ -77,18 +77,18 @@ enum
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#define GET_OP(ctx, op, val) { \
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#define GET_OP(ctx, op, val) { \
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SHEMU_STATUS status = ShemuX86GetOperandValue(ctx, op, val); \
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shstatus = ShemuX86GetOperandValue(ctx, op, val); \
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if (SHEMU_SUCCESS != status) \
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if (SHEMU_SUCCESS != shstatus) \
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{ \
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{ \
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return status; \
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return shstatus; \
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} \
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} \
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}
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}
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#define SET_OP(ctx, op, val) { \
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#define SET_OP(ctx, op, val) { \
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SHEMU_STATUS status = ShemuX86SetOperandValue(ctx, op, val); \
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shstatus = ShemuX86SetOperandValue(ctx, op, val); \
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if (SHEMU_SUCCESS != status) \
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if (SHEMU_SUCCESS != shstatus) \
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{ \
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{ \
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return status; \
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return shstatus; \
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} \
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} \
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}
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}
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@ -1448,20 +1448,23 @@ ShemuX86Multiply64Unsigned(
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ND_UINT64 *ResLow
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ND_UINT64 *ResLow
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)
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)
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{
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{
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ND_UINT64 xLow = (ND_UINT64)(ND_UINT32)Operand1;
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ND_UINT64 xLow, xHigh, yLow, yHigh, p0, p1, p2, p3, ps;
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ND_UINT64 xHigh = Operand1 >> 32;
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ND_UINT64 yLow = (ND_UINT64)(ND_UINT32)Operand2;
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ND_UINT64 yHigh = Operand2 >> 32;
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ND_UINT64 p0 = xLow * yLow;
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xLow = Operand1 & 0xFFFFFFFF;
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ND_UINT64 p1 = xLow * yHigh;
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xHigh = Operand1 >> 32;
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ND_UINT64 p2 = xHigh * yLow;
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yLow = Operand2 & 0xFFFFFFFF;
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ND_UINT64 p3 = xHigh * yHigh;
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yHigh = Operand2 >> 32;
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ND_UINT32 cy = (ND_UINT32)(((p0 >> 32) + (ND_UINT32)p1 + (ND_UINT32)p2) >> 32);
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// Multiply the 4 parts into 4 partial products.
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p0 = xLow * yLow;
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p1 = xLow * yHigh;
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p2 = xHigh * yLow;
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p3 = xHigh * yHigh;
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ps = (((p0 >> 32) + (p1 & 0xFFFFFFFF) + (p2 & 0xFFFFFFFF)) >> 32) & 0xFFFFFFFF;
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// Fill in the final result (low & high 64-bit parts).
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*ResLow = p0 + (p1 << 32) + (p2 << 32);
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*ResLow = p0 + (p1 << 32) + (p2 << 32);
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*ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + cy;
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*ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + ps;
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}
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}
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@ -1477,8 +1480,18 @@ ShemuX86Multiply64Signed(
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)
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)
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{
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{
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ShemuX86Multiply64Unsigned((ND_UINT64)Operand1, (ND_UINT64)Operand2, (ND_UINT64 *)ResHigh, (ND_UINT64 *)ResLow);
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ShemuX86Multiply64Unsigned((ND_UINT64)Operand1, (ND_UINT64)Operand2, (ND_UINT64 *)ResHigh, (ND_UINT64 *)ResLow);
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if (Operand1 < 0LL) *ResHigh -= Operand2;
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if (Operand2 < 0LL) *ResHigh -= Operand1;
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// Negate, if needed.
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if (Operand1 < 0)
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{
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*ResHigh -= Operand2;
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}
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// Negate, if needed.
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if (Operand2 < 0)
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{
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*ResHigh -= Operand1;
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}
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}
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}
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@ -2789,7 +2802,7 @@ check_far_branch:
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}
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}
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else
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else
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{
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{
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ShemuX86Multiply64Signed(dst.Value.Qwords[0], src.Value.Qwords[0],
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ShemuX86Multiply64Signed((ND_SINT64)dst.Value.Qwords[0], (ND_SINT64)src.Value.Qwords[0],
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(ND_SINT64*)&res.Value.Qwords[1], (ND_SINT64*)&res.Value.Qwords[0]);
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(ND_SINT64*)&res.Value.Qwords[1], (ND_SINT64*)&res.Value.Qwords[0]);
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}
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}
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}
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}
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@ -139,22 +139,22 @@ enum
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#define NDR_IA32_TSC_AUX 0xC0000103
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#define NDR_IA32_TSC_AUX 0xC0000103
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#define NDR_MSR_ANY 0xFFFFFFFF
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#define NDR_MSR_ANY 0xFFFFFFFF
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#define NDR_RFLAG_CF (1 << 0)
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#define NDR_RFLAG_CF (1ULL << 0)
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#define NDR_RFLAG_PF (1 << 2)
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#define NDR_RFLAG_PF (1ULL << 2)
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#define NDR_RFLAG_AF (1 << 4)
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#define NDR_RFLAG_AF (1ULL << 4)
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#define NDR_RFLAG_ZF (1 << 6)
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#define NDR_RFLAG_ZF (1ULL << 6)
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#define NDR_RFLAG_SF (1 << 7)
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#define NDR_RFLAG_SF (1ULL << 7)
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#define NDR_RFLAG_TF (1 << 8)
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#define NDR_RFLAG_TF (1ULL << 8)
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#define NDR_RFLAG_IF (1 << 9)
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#define NDR_RFLAG_IF (1ULL << 9)
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#define NDR_RFLAG_DF (1 << 10)
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#define NDR_RFLAG_DF (1ULL << 10)
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#define NDR_RFLAG_OF (1 << 11)
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#define NDR_RFLAG_OF (1ULL << 11)
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#define NDR_RFLAG_IOPL (3 << 12)
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#define NDR_RFLAG_IOPL (3ULL << 12)
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#define NDR_RFLAG_NT (1 << 14)
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#define NDR_RFLAG_NT (1ULL << 14)
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#define NDR_RFLAG_RF (1 << 16)
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#define NDR_RFLAG_RF (1ULL << 16)
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#define NDR_RFLAG_VM (1 << 17)
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#define NDR_RFLAG_VM (1ULL << 17)
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#define NDR_RFLAG_AC (1 << 18)
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#define NDR_RFLAG_AC (1ULL << 18)
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#define NDR_RFLAG_VIF (1 << 19)
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#define NDR_RFLAG_VIF (1ULL << 19)
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#define NDR_RFLAG_VIP (1 << 20)
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#define NDR_RFLAG_VIP (1ULL << 20)
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#define NDR_RFLAG_ID (1 << 21)
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#define NDR_RFLAG_ID (1ULL << 21)
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#endif
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#endif
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