arno/bddisasm
1
0
Fork 0
mirror of https://github.com/bitdefender/bddisasm.git synced 2024-12-01 11:58:19 +00:00
Code Issues Releases Wiki Activity
f9a36db25e
bddisasm/bdshemu_test/basic/test_64_loadrip02.result

33 lines
2.7 KiB
Plaintext
Raw Normal View History

Initial commit.
2020-07-21 08:19:18 +00:00
RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
RIP = 0x0000000000200000 RFLAGS = 0x0000000000000202
Emulating: 0x0000000000200000 FFREE st3
RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
RIP = 0x0000000000200002 RFLAGS = 0x0000000000000202
Emulating: 0x0000000000200002 FXSAVE [rsp]
RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
RSP = 0x0000000000101000 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
RIP = 0x0000000000200006 RFLAGS = 0x0000000000000202
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
Emulating: 0x0000000000200006 ADD rsp, 0x0000000000000008
Initial commit.
2020-07-21 08:19:18 +00:00
RAX = 0x0000000000000000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
RSP = 0x0000000000101008 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
RIP = 0x000000000020000a RFLAGS = 0x0000000000000202
Emulating: 0x000000000020000a MOV rax, qword ptr [rsp]
RAX = 0x0000000000200000 RCX = 0x0000000000000000 RDX = 0x0000000000000000 RBX = 0x0000000000000000
RSP = 0x0000000000101008 RBP = 0x0000000000000000 RSI = 0x0000000000000000 RDI = 0x0000000000000000
R8 = 0x0000000000000000 R9 = 0x0000000000000000 R10 = 0x0000000000000000 R11 = 0x0000000000000000
R12 = 0x0000000000000000 R13 = 0x0000000000000000 R14 = 0x0000000000000000 R15 = 0x0000000000000000
RIP = 0x000000000020000e RFLAGS = 0x0000000000000202
Emulating: 0x000000000020000e INT3
Emulation terminated with status 0x00000003, flags: 0x2, 0 NOPs
SHEMU_FLAG_LOAD_RIP
Reference in New Issue Copy Permalink