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bddisasm/bddisasm_test/x86/basic/vmx_64.result

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Initial commit.
2020-07-21 08:19:18 +00:00
0000000000000000 0f01c1 VMCALL
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup. Moved helper functions in bdhelpers.c. Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
2021-11-02 09:22:22 +00:00
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
0000000000000003 0f01d4 VMFUNC
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
0000000000000006 0f01c2 VMLAUNCH
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
0000000000000009 0f01c3 VMRESUME
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
000000000000000C 0f01c4 VMXOFF
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
000000000000000F 0f78c8 VMREAD rax, rcx
DSIZE: 64, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1
0000000000000012 670f7927 VMWRITE rsp, qword ptr [edi]
DSIZE: 64, ASIZE: 32, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 4, RegCount: 1
Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M,
Segment: 3, Base: 7,
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1
0000000000000016 0fc7b42400010000 VMPTRLD qword ptr [rsp+0x100]
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M,
Segment: 2, Base: 4, Displacement: 0x0000000000000100,
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
000000000000001E 670fc73f VMPTRST qword ptr [edi]
DSIZE: 32, ASIZE: 32, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M,
Segment: 3, Base: 7,
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
0000000000000022 660fc734c8 VMCLEAR qword ptr [rax+rcx*8]
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M,
Segment: 3, Base: 0, Index: 1 * 8,
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
0000000000000027 f30fc7342500100000 VMXON qword ptr [0x1000]
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M,
Segment: 3, Displacement: 0x0000000000001000,
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
0000000000000030 660f388006 INVEPT rax, xmmword ptr [rsi]
DSIZE: 64, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
Segment: 3, Base: 6,
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1
0000000000000035 660f38811424 INVVPID rdx, xmmword ptr [rsp]
DSIZE: 64, ASIZE: 64, VLEN: -
ISA Set: VTX, Ins cat: VTX, CET tracked: no
CPUID leaf: 0x00000001, reg: ecx, bit: 5
FLAGS access
CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0,
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: yes, Compat: no, Long: yes
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
2020-09-10 08:06:20 +00:00
SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes
VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no
Initial commit.
2020-07-21 08:19:18 +00:00
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1
Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
Segment: 2, Base: 4,
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1
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