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bddisasm/isagenerator/instructions/table_evex_1.dat

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Switched from nil to n/a naming for absent operands, as it is more obvious.
2023-02-08 15:44:45 +00:00
#
# Copyright (c) 2020 Bitdefender
# SPDX-License-Identifier: Apache-2.0
#
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x10 - 0x1F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VMOVUPS ; Vfv{K}{z},Wfv ; ; evex m:1 p:0 l:x w:0 0x10 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVUPD ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x10 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVSS ; Vdq{K}{z},Mss ; ; evex m:1 p:2 l:i w:0 0x10 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R
VMOVSS ; Vdq{K}{z},Hdq,Udq ; ; evex m:1 p:2 l:i w:0 0x10 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R
VMOVSD ; Vdq{K}{z},Msd ; ; evex m:1 p:3 l:i w:1 0x10 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R
VMOVSD ; Vdq{K}{z},Hdq,Udq ; ; evex m:1 p:3 l:i w:1 0x10 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R
VMOVUPS ; Wfv{K}{z},Vfv ; ; evex m:1 p:0 l:x w:0 0x11 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVUPD ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x11 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVSS ; Mss{K},Vdq ; ; evex m:1 p:2 l:i w:0 0x11 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R
VMOVSS ; Udq{K}{z},Hdq,Vdq ; ; evex m:1 p:2 l:i w:0 0x11 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R
VMOVSD ; Msd{K},Vdq ; ; evex m:1 p:3 l:i w:1 0x11 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R
VMOVSD ; Udq{K}{z},Hdq,Vdq ; ; evex m:1 p:3 l:i w:1 0x11 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R
VMOVLPS ; Vdq,Hdq,Mq ; ; evex m:1 p:0 l:0 w:0 0x12 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R
VMOVHLPS ; Vdq,Hdq,Udq ; ; evex m:1 p:0 l:0 w:0 0x12 /r:reg ; s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R
VMOVLPD ; Vdq,Hdq,Mq ; ; evex m:1 p:1 l:0 w:1 0x12 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R
VMOVSLDUP ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:0 0x12 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R
VMOVDDUP ; Vdq{K}{z},Wq ; ; evex m:1 p:3 l:0 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R
VMOVDDUP ; Vqq{K}{z},Wqq ; ; evex m:1 p:3 l:1 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R
VMOVDDUP ; Voq{K}{z},Woq ; ; evex m:1 p:3 l:2 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R
VMOVLPS ; Mq,Vdq ; ; evex m:1 p:0 l:0 w:0 0x13 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R
VMOVLPD ; Mq,Vdq ; ; evex m:1 p:1 l:0 w:1 0x13 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VUNPCKLPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VUNPCKLPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VUNPCKHPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VUNPCKHPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VMOVHPS ; Vdq,Hdq,Mq ; ; evex m:1 p:0 l:0 w:0 0x16 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R
VMOVLHPS ; Vdq,Hdq,Udq ; ; evex m:1 p:0 l:0 w:0 0x16 /r:reg ; s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R
VMOVHPD ; Vdq,Hdq,Mq ; ; evex m:1 p:1 l:0 w:1 0x16 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R
VMOVSHDUP ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:0 0x16 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R
VMOVHPS ; Mq,Vdq ; ; evex m:1 p:0 l:0 w:0 0x17 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R
VMOVHPD ; Mq,Vdq ; ; evex m:1 p:1 l:0 w:1 0x17 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x20 - 0x2F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VMOVAPS ; Vfv{K}{z},Wfv ; ; evex m:1 p:0 l:x w:0 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVAPD ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVAPS ; Wfv{K}{z},Vfv ; ; evex m:1 p:0 l:x w:0 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVAPD ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VCVTSI2SS ; Vdq,Hdq{er},Ey ; ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VCVTSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64
VCVTSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VMOVNTPS ; Mfv,Vfv ; ; evex m:1 p:0 l:x w:0 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
VMOVNTPD ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:1 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
VCVTTSS2SI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTTSD2SI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
2023-02-09 08:54:45 +00:00
VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x50 - 0x5F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VANDPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VANDPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VANDNPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VANDNPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VXORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VXORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R
VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R
VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x60 - 0x6F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPUNPCKLBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:x 0x60 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPUNPCKLWD ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:x 0x61 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPUNPCKLDQ ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x62 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPACKSSWB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x63 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPCMPGTB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x64 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPCMPGTW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x65 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPCMPGTD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x66 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPACKUSWB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x67 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPUNPCKHBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x68 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPUNPCKHWD ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x69 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPUNPCKHDQ ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x6A /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPACKSSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x6B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPUNPCKLQDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x6C /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPUNPCKHQDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x6D /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VMOVD ; Vdq,Ed ; ; evex m:1 p:1 l:0 w:0 0x6E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVQ ; Vdq,Eq ; ; evex m:1 p:1 l:0 w:1 0x6E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVDQA32 ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:0 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQA64 ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQU32 ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:0 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVDQU64 ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:1 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVDQU8 ; Vfv{K}{z},Wfv ; ; evex m:1 p:3 l:x w:0 0x6F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVDQU16 ; Vfv{K}{z},Wfv ; ; evex m:1 p:3 l:x w:1 0x6F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x70 - 0x7F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPSHUFD ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x70 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPSHUFHW ; Vfv{K}{z},Wfv,Ib ; ; evex m:1 p:2 l:x w:i 0x70 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPSHUFLW ; Vfv{K}{z},Wfv,Ib ; ; evex m:1 p:3 l:x w:i 0x70 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
VPSRLW ; Hfv{K}{z},Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x71 /2 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSRAW ; Hfv{K}{z},Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x71 /4 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSLLW ; Hfv{K}{z},Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x71 /6 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPRORD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /0 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPRORQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x72 /0 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPROLD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /1 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPROLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x72 /1 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSRLD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /2 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSRAD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /4 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSRAQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x72 /4 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSLLD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSRLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /2 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSRLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /3 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R
VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSLLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R
VPCMPEQB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:1 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:1 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPCMPEQW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTTSS2USI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTTSD2USI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTSS2USI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTSD2USI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTUDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTUSI2SS ; Vss,Hss{er},Ey ; ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64
VCVTUSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VMOVD ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVQ ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VMOVD ; Vdq,Wd ; ; evex m:1 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s, e:E9NF, w:W|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VMOVQ ; Vdq,Wq ; ; evex m:1 p:2 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VMOVDQA32 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQA64 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQU32 ; Wfv{K}{z},Vfv ; ; evex m:1 p:2 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVDQU64 ; Wfv{K}{z},Vfv ; ; evex m:1 p:2 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVDQU8 ; Wfv{K}{z},Vfv ; ; evex m:1 p:3 l:x w:0 0x7F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
VMOVDQU16 ; Wfv{K}{z},Vfv ; ; evex m:1 p:3 l:x w:1 0x7F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x80 - 0x8F
# 0x90 - 0x9F
# 0xA0 - 0xAF
# 0xB0 - 0xBF
# 0xC0 - 0xCF
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VPINSRW ; Vdq,Hdq,Mw,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R
VPINSRW ; Vdq,Hdq,Rv,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R
VPEXTRW ; Gy,Udq,Ib ; ; evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VSHUFPS ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:1 p:0 l:x w:0 0xC6 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFPD ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0xC6 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xD0 - 0xDF
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPSRLW ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R
VPSRLD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 0xD2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPSRLQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xD3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPADDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xD4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPMULLW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VMOVD ; Wd,Vdq ; ; evex m:1 p:1 l:0 w:0 0xD6 /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s, e:E9NF, w:W|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VMOVQ ; Wq,Vdq ; ; evex m:1 p:1 l:0 w:1 0xD6 /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VPSUBUSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R
VPSUBUSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R
VPMINUB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDA /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPANDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xDB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPANDD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xDB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPADDUSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPADDUSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDD /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPMAXUB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDE /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPANDND ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xDF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPANDNQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xDF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xE0 - 0xEF
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPAVGB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE0 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSRAW ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:i 0xE1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R
VPSRAD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 0xE2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPSRAQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xE2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPAVGW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPMULHUW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPMULHW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0xE6 /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VMOVNTDQ ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:0 0xE7 /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
VPSUBSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSUBSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPMINSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xEA /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPORD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xEB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPORQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xEB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPADDSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xEC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPADDSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xED /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPMAXSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xEE /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPXORD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xEF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPXORQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xEF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xF0 - 0xFF
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPSLLW ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:i 0xF1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R
VPSLLD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 0xF2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPSLLQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xF3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPMULUDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xF4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPMADDWD ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSADBW ; Vfv,Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF6 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R
VPSUBB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSUBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPSUBD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xFA /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSUBQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xFB /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPADDB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xFC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPADDW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xFD /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPADDD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xFE /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
# APX - KMOV instructions.
KMOVW ; rKw,Mw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVB ; rKb,Mb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVQ ; rKq,Mq ; ; evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVD ; rKd,Md ; ; evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVW ; rKw,mKw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVB ; rKb,mKb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVQ ; rKq,mKq ; ; evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVD ; rKd,mKd ; ; evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVW ; Mw,rKw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVB ; Mb,rKb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVQ ; Mq,rKq ; ; evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVD ; Md,rKd ; ; evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVW ; rKw,Ry ; ; evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVB ; rKb,Ry ; ; evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVQ ; rKq,Ry ; ; evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVD ; rKd,Ry ; ; evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVW ; Gy,mKw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVB ; Gy,mKb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVQ ; Gy,mKq ; ; evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
KMOVD ; Gy,mKd ; ; evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV
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