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bddisasm/bddisasm_test/x86/msr/msr_64.result

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Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
0000000000000000 c4e77bf6c0bdbdbdbd RDMSR rax, 0xbdbdbdbd
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
DSIZE: 32, ASIZE: 64, VLEN: -
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
0000000000000009 62f77f08f6c0bdbdbdbd RDMSR rax, 0xbdbdbdbd
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
EVEX Tuple Type: None
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
0000000000000013 f20f01c6 RDMSRLIST
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: MSRLIST, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 27
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: S,
Base: 6,
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
Operand: 1, Acc: -W, Type: Memory, Size: 512, RawSize: 512, Encoding: S,
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Base: 7,
Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
0000000000000017 0f01c6 WRMSRNS
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: WRMSRNS, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 19
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) * Add support for SIMD exceptions reporting in INSTRUX. * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
2024-11-07 10:15:29 +00:00
000000000000001A c4e77af6c0bdbdbdbd WRMSRNS 0xbdbdbdbd, rax
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
0000000000000023 62f77e08f6c0bdbdbdbd WRMSRNS 0xbdbdbdbd, rax
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
EVEX Tuple Type: None
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
000000000000002D f30f01c6 WRMSRLIST
DSIZE: 32, ASIZE: 64, VLEN: -
ISA Set: MSRLIST, Ins cat: SYSTEM, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 27
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: S,
Base: 6,
Operand: 1, Acc: R-, Type: Memory, Size: 512, RawSize: 512, Encoding: S,
Base: 7,
Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
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