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39 lines
1.3 KiB
39 lines
1.3 KiB
From 46e3e699294d3fe4fecb08d697bb29addab29576 Mon Sep 17 00:00:00 2001
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From: Zhao Yakui <yakui.zhao@intel.com>
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Date: Fri, 28 May 2010 20:28:41 +0800
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Subject: [PATCH 4/4] drm/i915: Configure the PIPECONF dither correctly for eDP
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The non-8 BPC can be used for the eDP output device that is connected through
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DP-A or DP-D on PCH. In such case we should set the PIPECONF dither correctly.
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Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
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1 files changed, 11 insertions(+), 0 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index 32ae849..49c9663 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -3239,6 +3239,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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/* setup pipeconf */
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pipeconf = I915_READ(pipeconf_reg);
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+ if (HAS_PCH_SPLIT(dev) && (is_edp || intel_edp_is_pch(crtc))) {
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+ /* configure the dither correctly for eDP */
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+ pipeconf &= ~PIPE_DITHER_TYPE_MASK;
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+ if ((pipeconf & PIPE_BPC_MASK) != PIPE_8BPC) {
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+ pipeconf |= PIPE_ENABLE_DITHER;
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+ pipeconf |= PIPE_DITHER_TYPE_ST01;
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+ } else {
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+ pipeconf &= ~PIPE_ENABLE_DITHER;
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+ }
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+ }
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+
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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--
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1.7.0.1
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