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430 lines
12 KiB
430 lines
12 KiB
From 152d92c3e618d1c17c6a84c66aec00af227c3f0e Mon Sep 17 00:00:00 2001
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From: Jesse Barnes <jbarnes@virtuousgeek.org>
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Date: Tue, 4 Jan 2011 15:09:30 -0800
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Subject: [PATCH 3/3] drm/i915: add pipe/plane enable/disable functions
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Add plane enable/disable functions to prevent duplicated code and allow
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us to easily check for plane enable/disable requirements (such as pipe
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enable, plane status, pll status etc).
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Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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---
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drivers/gpu/drm/i915/i915_reg.h | 5 +-
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drivers/gpu/drm/i915/intel_display.c | 308 +++++++++++++++++++++++-----------
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2 files changed, 216 insertions(+), 97 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index 12c547a..b0f1290 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -2537,9 +2537,10 @@
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#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
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#define DISPPLANE_STEREO_ENABLE (1<<25)
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#define DISPPLANE_STEREO_DISABLE 0
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-#define DISPPLANE_SEL_PIPE_MASK (1<<24)
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+#define DISPPLANE_SEL_PIPE_SHIFT 24
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+#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
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#define DISPPLANE_SEL_PIPE_A 0
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-#define DISPPLANE_SEL_PIPE_B (1<<24)
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+#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
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#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
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#define DISPPLANE_SRC_KEY_DISABLE 0
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#define DISPPLANE_LINE_DOUBLE (1<<20)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index 711beca..cef853b 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -1058,6 +1058,203 @@ void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
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}
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}
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+static const char *state_string(bool enabled)
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+{
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+ return enabled ? "on" : "off";
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+}
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+
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+/* Only for pre-ILK configs */
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+static void assert_pll(struct drm_i915_private *dev_priv,
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+ enum pipe pipe, bool state)
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+{
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+ int reg;
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+ u32 val;
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+ bool cur_state;
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+
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+ reg = DPLL(pipe);
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+ val = I915_READ(reg);
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+ cur_state = !!(val & DPLL_VCO_ENABLE);
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+ WARN(cur_state != state,
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+ "PLL state assertion failure (expected %s, current %s)\n",
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+ state_string(state), state_string(cur_state));
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+}
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+#define assert_pll_enabled(d, p) assert_pll(d, p, true)
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+#define assert_pll_disabled(d, p) assert_pll(d, p, false)
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+
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+static void assert_pipe_enabled(struct drm_i915_private *dev_priv,
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+ enum pipe pipe)
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+{
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+ int reg;
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+ u32 val;
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+
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+ reg = PIPECONF(pipe);
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+ val = I915_READ(reg);
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+ WARN(!(val & PIPECONF_ENABLE),
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+ "pipe %c assertion failure, should be active but is disabled\n",
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+ pipe ? 'B' : 'A');
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+}
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+
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+static void assert_plane_enabled(struct drm_i915_private *dev_priv,
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+ enum plane plane)
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+{
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+ int reg;
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+ u32 val;
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+
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+ reg = DSPCNTR(plane);
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+ val = I915_READ(reg);
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+ WARN(!(val & DISPLAY_PLANE_ENABLE),
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+ "plane %c assertion failure, should be active but is disabled\n",
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+ plane ? 'B' : 'A');
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+}
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+
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+static void assert_planes_disabled(struct drm_i915_private *dev_priv,
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+ enum pipe pipe)
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+{
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+ int reg, i;
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+ u32 val;
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+ int cur_pipe;
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+
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+ /* Need to check both planes against the pipe */
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+ for (i = 0; i < 2; i++) {
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+ reg = DSPCNTR(i);
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+ val = I915_READ(reg);
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+ cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
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+ DISPPLANE_SEL_PIPE_SHIFT;
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+ WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
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+ "plane %d assertion failure, should be off on pipe %c but is still active\n",
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+ i, pipe ? 'B' : 'A');
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+ }
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+}
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+
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+/**
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+ * intel_enable_pipe - enable a pipe, assertiing requirements
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+ * @dev_priv: i915 private structure
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+ * @pipe: pipe to enable
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+ *
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+ * Enable @pipe, making sure that various hardware specific requirements
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+ * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
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+ *
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+ * @pipe should be %PIPE_A or %PIPE_B.
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+ *
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+ * Will wait until the pipe is actually running (i.e. first vblank) before
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+ * returning.
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+ */
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+static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
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+{
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+ int reg;
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+ u32 val;
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+
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+ /*
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+ * A pipe without a PLL won't actually be able to drive bits from
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+ * a plane. On ILK+ the pipe PLLs are integrated, so we don't
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+ * need the check.
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+ */
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+ if (!HAS_PCH_SPLIT(dev_priv->dev))
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+ assert_pll_enabled(dev_priv, pipe);
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+
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+ reg = PIPECONF(pipe);
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+ val = I915_READ(reg);
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+ val |= PIPECONF_ENABLE;
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+ I915_WRITE(reg, val);
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+ POSTING_READ(reg);
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+ intel_wait_for_vblank(dev_priv->dev, pipe);
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+}
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+
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+/**
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+ * intel_disable_pipe - disable a pipe, assertiing requirements
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+ * @dev_priv: i915 private structure
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+ * @pipe: pipe to disable
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+ *
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+ * Disable @pipe, making sure that various hardware specific requirements
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+ * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
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+ *
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+ * @pipe should be %PIPE_A or %PIPE_B.
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+ *
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+ * Will wait until the pipe has shut down before returning.
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+ */
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+static void intel_disable_pipe(struct drm_i915_private *dev_priv,
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+ enum pipe pipe)
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+{
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+ int reg;
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+ u32 val;
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+
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+ /*
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+ * Make sure planes won't keep trying to pump pixels to us,
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+ * or we might hang the display.
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+ */
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+ assert_planes_disabled(dev_priv, pipe);
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+
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+ /* Don't disable pipe A or pipe A PLLs if needed */
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+ if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
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+ return;
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+
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+ reg = PIPECONF(pipe);
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+ val = I915_READ(reg);
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+ val &= ~PIPECONF_ENABLE;
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+ I915_WRITE(reg, val);
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+ POSTING_READ(reg);
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+ intel_wait_for_pipe_off(dev_priv->dev, pipe);
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+}
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+
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+/**
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+ * intel_enable_plane - enable a display plane on a given pipe
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+ * @dev_priv: i915 private structure
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+ * @plane: plane to enable
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+ * @pipe: pipe being fed
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+ *
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+ * Enable @plane on @pipe, making sure that @pipe is running first.
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+ */
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+static void intel_enable_plane(struct drm_i915_private *dev_priv,
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+ enum plane plane, enum pipe pipe)
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+{
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+ int reg;
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+ u32 val;
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+
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+ /* If the pipe isn't enabled, we can't pump pixels and may hang */
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+ assert_pipe_enabled(dev_priv, pipe);
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+
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+ reg = DSPCNTR(plane);
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+ val = I915_READ(reg);
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+ val |= DISPLAY_PLANE_ENABLE;
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+ I915_WRITE(reg, val);
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+ POSTING_READ(reg);
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+ intel_wait_for_vblank(dev_priv->dev, pipe);
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+}
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+
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+/*
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+ * Plane regs are double buffered, going from enabled->disabled needs a
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+ * trigger in order to latch. The display address reg provides this.
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+ */
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+static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
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+ enum plane plane)
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+{
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+ u32 reg = DSPADDR(plane);
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+ I915_WRITE(reg, I915_READ(reg));
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+}
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+
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+/**
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+ * intel_disable_plane - disable a display plane
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+ * @dev_priv: i915 private structure
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+ * @plane: plane to disable
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+ * @pipe: pipe consuming the data
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+ *
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+ * Disable @plane; should be an independent operation.
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+ */
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+static void intel_disable_plane(struct drm_i915_private *dev_priv,
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+ enum plane plane, enum pipe pipe)
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+{
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+ int reg;
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+ u32 val;
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+
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+ reg = DSPCNTR(plane);
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+ val = I915_READ(reg);
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+ val &= ~DISPLAY_PLANE_ENABLE;
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+ I915_WRITE(reg, val);
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+ POSTING_READ(reg);
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+ intel_flush_display_plane(dev_priv, plane);
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+ intel_wait_for_vblank(dev_priv->dev, pipe);
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+}
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+
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static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
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struct drm_device *dev = crtc->dev;
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@@ -2003,14 +2200,6 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
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}
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}
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-static void intel_flush_display_plane(struct drm_device *dev,
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- int plane)
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-{
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- struct drm_i915_private *dev_priv = dev->dev_private;
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- u32 reg = DSPADDR(plane);
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- I915_WRITE(reg, I915_READ(reg));
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-}
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-
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/*
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* When we disable a pipe, we need to clear any pending scanline wait events
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* to avoid hanging the ring, which we assume we are waiting on.
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@@ -2158,22 +2347,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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dev_priv->pch_pf_size);
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}
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- /* Enable CPU pipe */
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- reg = PIPECONF(pipe);
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- temp = I915_READ(reg);
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- if ((temp & PIPECONF_ENABLE) == 0) {
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- I915_WRITE(reg, temp | PIPECONF_ENABLE);
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- POSTING_READ(reg);
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- intel_wait_for_vblank(dev, intel_crtc->pipe);
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- }
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-
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- /* configure and enable CPU plane */
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- reg = DSPCNTR(plane);
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- temp = I915_READ(reg);
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- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
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- I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
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- intel_flush_display_plane(dev, plane);
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- }
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+ intel_enable_pipe(dev_priv, pipe);
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+ intel_enable_plane(dev_priv, plane, pipe);
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/* Skip the PCH stuff if possible */
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if (!is_pch_port)
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@@ -2285,27 +2460,13 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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drm_vblank_off(dev, pipe);
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intel_crtc_update_cursor(crtc, false);
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- /* Disable display plane */
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- reg = DSPCNTR(plane);
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- temp = I915_READ(reg);
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- if (temp & DISPLAY_PLANE_ENABLE) {
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- I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
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- intel_flush_display_plane(dev, plane);
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- }
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+ intel_disable_plane(dev_priv, plane, pipe);
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if (dev_priv->cfb_plane == plane &&
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dev_priv->display.disable_fbc)
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dev_priv->display.disable_fbc(dev);
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- /* disable cpu pipe, disable after all planes disabled */
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- reg = PIPECONF(pipe);
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- temp = I915_READ(reg);
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- if (temp & PIPECONF_ENABLE) {
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- I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
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- POSTING_READ(reg);
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- /* wait for cpu pipe off, pipe state */
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- intel_wait_for_pipe_off(dev, intel_crtc->pipe);
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- }
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+ intel_disable_pipe(dev_priv, pipe);
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/* Disable PF */
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I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
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@@ -2500,19 +2661,8 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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udelay(150);
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}
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- /* Enable the pipe */
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- reg = PIPECONF(pipe);
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- temp = I915_READ(reg);
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- if ((temp & PIPECONF_ENABLE) == 0)
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- I915_WRITE(reg, temp | PIPECONF_ENABLE);
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-
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- /* Enable the plane */
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- reg = DSPCNTR(plane);
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- temp = I915_READ(reg);
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- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
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- I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
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- intel_flush_display_plane(dev, plane);
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- }
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+ intel_enable_pipe(dev_priv, pipe);
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+ intel_enable_plane(dev_priv, plane, pipe);
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intel_crtc_load_lut(crtc);
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intel_update_fbc(dev);
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@@ -2544,33 +2694,13 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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dev_priv->display.disable_fbc)
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dev_priv->display.disable_fbc(dev);
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- /* Disable display plane */
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- reg = DSPCNTR(plane);
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- temp = I915_READ(reg);
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- if (temp & DISPLAY_PLANE_ENABLE) {
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- I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
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- /* Flush the plane changes */
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- intel_flush_display_plane(dev, plane);
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-
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- /* Wait for vblank for the disable to take effect */
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- if (IS_GEN2(dev))
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- intel_wait_for_vblank(dev, pipe);
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- }
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+ intel_disable_plane(dev_priv, plane, pipe);
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/* Don't disable pipe A or pipe A PLLs if needed */
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if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
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goto done;
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- /* Next, disable display pipes */
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- reg = PIPECONF(pipe);
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- temp = I915_READ(reg);
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- if (temp & PIPECONF_ENABLE) {
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- I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
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-
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- /* Wait for the pipe to turn off */
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- POSTING_READ(reg);
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- intel_wait_for_pipe_off(dev, pipe);
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- }
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+ intel_disable_pipe(dev_priv, pipe);
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reg = DPLL(pipe);
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temp = I915_READ(reg);
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@@ -4322,11 +4452,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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pipeconf &= ~PIPECONF_DOUBLE_WIDE;
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}
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- if (!HAS_PCH_SPLIT(dev)) {
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- dspcntr |= DISPLAY_PLANE_ENABLE;
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- pipeconf |= PIPECONF_ENABLE;
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+ if (!HAS_PCH_SPLIT(dev))
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dpll |= DPLL_VCO_ENABLE;
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- }
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DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
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drm_mode_debug_printmodeline(mode);
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@@ -4535,6 +4662,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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I915_WRITE(PIPECONF(pipe), pipeconf);
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POSTING_READ(PIPECONF(pipe));
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+ if (!HAS_PCH_SPLIT(dev))
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+ intel_enable_pipe(dev_priv, pipe);
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intel_wait_for_vblank(dev, pipe);
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@@ -4545,6 +4674,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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I915_WRITE(DSPCNTR(plane), dspcntr);
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+ POSTING_READ(DSPCNTR(plane));
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+ if (!HAS_PCH_SPLIT(dev))
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+ intel_enable_plane(dev_priv, plane, pipe);
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ret = intel_pipe_set_base(crtc, x, y, old_fb);
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@@ -5694,22 +5826,8 @@ static void intel_sanitize_modesetting(struct drm_device *dev,
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pipe = !pipe;
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/* Disable the plane and wait for it to stop reading from the pipe. */
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- I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
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- intel_flush_display_plane(dev, plane);
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-
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- if (IS_GEN2(dev))
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- intel_wait_for_vblank(dev, pipe);
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-
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- if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
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- return;
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-
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- /* Switch off the pipe. */
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- reg = PIPECONF(pipe);
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- val = I915_READ(reg);
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- if (val & PIPECONF_ENABLE) {
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- I915_WRITE(reg, val & ~PIPECONF_ENABLE);
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- intel_wait_for_pipe_off(dev, pipe);
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- }
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+ intel_disable_plane(dev_priv, plane, pipe);
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+ intel_disable_pipe(dev_priv, pipe);
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}
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static void intel_crtc_init(struct drm_device *dev, int pipe)
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--
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1.7.6.5
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