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104 lines
3.0 KiB
104 lines
3.0 KiB
From: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
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Subject: detect oprofile counters reserved by bios
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References: FATE#307426
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Patch-mainline: pending
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Signed-off-by: Tony Jones <tonyj@suse.de>
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Currently, oprofile fails silently on platforms where a non-OS entity such as
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the system firmware "enables" and uses a performance counter. The patch below
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suggests a workaround to the user in such instances.
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The patch below has been well tested on AMD and Intel based platforms. It
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improves on a previous version via better macro usage, use of rdmsrl and more
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accurate/informative error messages.
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Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
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Tested-by: Shashi Belur <shashi-kiran.belur@hp.com>
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---
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---
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arch/x86/oprofile/nmi_int.c | 58 ++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 58 insertions(+)
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--- a/arch/x86/oprofile/nmi_int.c
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+++ b/arch/x86/oprofile/nmi_int.c
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@@ -27,6 +27,19 @@
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#include "op_counter.h"
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#include "op_x86_model.h"
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+static const char RSVD_MSG[] =
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+ KERN_INFO "oprofile: performance counter #%d may already be"
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+ " reserved."
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+ " For counter #%d, EvntSel 0x%lx has value: 0x%llx.\n";
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+static const char PMC_MSG[] =
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+ KERN_INFO "oprofile: if oprofile doesn't collect data, then"
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+ " try using a different performance counter on your platform"
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+ " to monitor the desired event."
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+ " Delete counter #%d from the desired event by editing the"
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+ " /usr/share/oprofile/%s/<cpu>/events file."
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+ " If the event cannot be monitored by any other counter,"
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+ " contact your hardware or BIOS vendor.\n";
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+
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static struct op_x86_model_spec *model;
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static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
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static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
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@@ -466,6 +479,50 @@ static struct notifier_block oprofile_cp
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.notifier_call = oprofile_cpu_notifier
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};
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+#define P4_CCCR_ENABLE (1 << 12)
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+
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+/* check if the counter/evtsel is already enabled, say, by firmware */
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+static void nmi_is_counter_enabled(struct op_msrs * const msrs)
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+{
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+ __u8 vendor = boot_cpu_data.x86_vendor;
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+ __u8 family = boot_cpu_data.x86;
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+ u64 val;
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+ unsigned int i;
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+ char *arch = "arch";
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+
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+ /* Fill in at least the "arch" value to help the user */
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+ if (vendor == X86_VENDOR_AMD) {
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+ if (family == 6)
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+ arch = "i386";
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+ else
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+ arch = "x86-64";
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+ } else if (vendor == X86_VENDOR_INTEL) {
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+ arch = "i386";
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+ }
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+
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+ for (i = 0; i < model->num_controls; ++i) {
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+ if (!counter_config[i].enabled)
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+ continue;
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+ rdmsrl(msrs->controls[i].addr, val);
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+
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+ /* P4 is special. Other Intel, and all AMD CPUs
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+ ** are consistent in using "bit 22" as "enable"
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+ */
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+ if ((vendor == X86_VENDOR_INTEL) && (family == 0xf)) {
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+ if (val & P4_CCCR_ENABLE)
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+ goto err_rsvd;
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+ } else if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
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+ goto err_rsvd;
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+ }
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+ }
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+ return;
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+
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+err_rsvd:
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+ printk(RSVD_MSG, i, i, msrs->controls[i].addr, val);
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+ printk(PMC_MSG, i, arch);
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+ return;
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+}
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+
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static int nmi_setup(void)
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{
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int err = 0;
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@@ -483,6 +540,7 @@ static int nmi_setup(void)
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if (err)
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goto fail;
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+ nmi_is_counter_enabled(&per_cpu(cpu_msrs, 0));
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for_each_possible_cpu(cpu) {
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if (!cpu)
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continue;
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