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61 lines
1.8 KiB
61 lines
1.8 KiB
From: Kyle McMartin <kmcmartin@redhat.com>
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Date: Tue, 30 Sep 2014 16:19:47 -0400
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Subject: [PATCH] arm: highbank l2 reverts
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Revert some v3.16 changes to mach-highbank which broke L2 cache enablement.
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Will debug upstream separately, but we need F22/21 running there. (#1139762)
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---
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arch/arm/mach-highbank/highbank.c | 21 ++++++++++++---------
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1 file changed, 12 insertions(+), 9 deletions(-)
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diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
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index 8c35ae4ff176..38e1dc3b4c6e 100644
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--- a/arch/arm/mach-highbank/highbank.c
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+++ b/arch/arm/mach-highbank/highbank.c
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@@ -51,13 +51,11 @@ static void __init highbank_scu_map_io(void)
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}
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-static void highbank_l2c310_write_sec(unsigned long val, unsigned reg)
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+static void highbank_l2x0_disable(void)
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{
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- if (reg == L2X0_CTRL)
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- highbank_smc1(0x102, val);
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- else
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- WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n",
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- reg);
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+ outer_flush_all();
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+ /* Disable PL310 L2 Cache controller */
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+ highbank_smc1(0x102, 0x0);
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}
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static void __init highbank_init_irq(void)
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@@ -66,6 +64,14 @@ static void __init highbank_init_irq(void)
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if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
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highbank_scu_map_io();
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+
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+ /* Enable PL310 L2 Cache controller */
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+ if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
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+ of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
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+ highbank_smc1(0x102, 0x1);
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+ l2x0_of_init(0, ~0);
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+ outer_cache.disable = highbank_l2x0_disable;
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+ }
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}
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static void highbank_power_off(void)
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@@ -179,9 +185,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
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#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
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.dma_zone_size = (4ULL * SZ_1G),
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#endif
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- .l2c_aux_val = 0,
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- .l2c_aux_mask = ~0,
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- .l2c_write_sec = highbank_l2c310_write_sec,
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.init_irq = highbank_init_irq,
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.init_machine = highbank_init,
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.dt_compat = highbank_match,
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--
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1.9.3
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