From 46e3e699294d3fe4fecb08d697bb29addab29576 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Fri, 28 May 2010 20:28:41 +0800
Subject: [PATCH 4/4] drm/i915: Configure the PIPECONF dither correctly for eDP

The non-8 BPC can be used for the eDP output device that is connected through
DP-A or DP-D on PCH. In such case we should set the PIPECONF dither correctly.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 32ae849..49c9663 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3239,6 +3239,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 	/* setup pipeconf */
 	pipeconf = I915_READ(pipeconf_reg);
 
+	if (HAS_PCH_SPLIT(dev) && (is_edp || intel_edp_is_pch(crtc))) {
+		/* configure the dither correctly for eDP */
+		pipeconf &= ~PIPE_DITHER_TYPE_MASK;
+		if ((pipeconf & PIPE_BPC_MASK) != PIPE_8BPC) {
+			pipeconf |= PIPE_ENABLE_DITHER;
+			pipeconf |= PIPE_DITHER_TYPE_ST01;
+		} else {
+			pipeconf &= ~PIPE_ENABLE_DITHER;
+		}
+	}
+
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 
-- 
1.7.0.1

